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PDF CDB42448 Data sheet ( Hoja de datos )

Número de pieza CDB42448
Descripción 8-Out CODEC
Fabricantes Cirrus Logic　
Logotipo Cirrus Logic Logotipo



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No Preview Available ! CDB42448 Hoja de datos, Descripción, Manual

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CS42888
108 dB, 192 kHz 4-In, 8-Out CODEC
FEATURES
 Four 24-bit A/D, Eight 24-bit D/A Converters
 ADC Dynamic Range
– 105 dB Differential
– 102 dB Single-Ended
 DAC Dynamic Range
– 108 dB Differential
– 105 dB Single-Ended
 ADC/DAC THD+N
– -98 dB Differential
– -95 dB Single-Ended
 Compatible with Industry-Standard Time
Division Multiplexed (TDM) Serial Interface
 System Sampling Rates up to 192 kHz
 Programmable ADC High-Pass Filter for DC
Offset Calibration
 Logarithmic Digital Volume Control
 I²C® & SPI™ Host Control Port
 Supports Logic Levels Between 5 V and 1.8 V
 Popguard® Technology
GENERAL DESCRIPTION
The CS42888 CODEC provides four multi-bit analog-to-
digital and eight multi-bit digital-to-analog delta-sigma
converters. The CODEC is capable of operation with ei-
ther differential or single-ended inputs and outputs, in a
64-pin LQFP package.
Four fully differential, or single-ended, inputs are avail-
able on stereo ADC1 and ADC2. Digital volume control
is provided for each ADC channel, with selectable over-
flow detection.
All eight DAC channels provide digital volume control
and can operate with differential or single-ended
outputs.
An auxiliary serial input is available for an additional two
channels of PCM data.
The CS42888 is available in a 64-pin LQFP package in
Commercial (-10° to +70°) and Automotive (-40° to
+105°) grades. The CDB42888 Customer Demonstra-
tion board is also available for device evaluation and
implementation suggestions. Please refer to “Ordering
Information” on page 61 for complete ordering
information.
The CS42888 is ideal for audio systems requiring wide
dynamic range, negligible distortion and low noise, such
as A/V receivers, DVD receivers, and automotive audio
systems.
Control Port & Serial
Audio Port Supply =
1.8 V to 5 V
Digital Supply =
3.3 V to 5 V
I2C/SPI
Software Mode
Control Data
Interrupt
Reset
Register
Configuration
ADC Overflow
& Clock Error
Interrupt
Analog Supply =
3.3 V to 5 V
Internal Voltage
Reference
External
Mute Control
Mute
Control
Serial Audio
Input
Auxilliary Serial
Audio Input
Input Master
Clock
Serial Audio
Output
Volume
Controls
Digital
Filters
∆Σ
Modulators
High Pass
Filter
High Pass
Filter
Digital
Filters
Digital
Filters
Multibit
DAC1-4 and
8
Differential or
Single-Ended
Analog Filters
Outputs
8
Multibit
Oversampling
ADC1
Multibit
Oversampling
ADC2
2
2 Differential or Single-
Ended Analog Inputs
2
2
http://www.cirrus.com
Copyright © Cirrus Logic, Inc. 2006
(All Rights Reserved)
AUGUST '06
DS717F1

1 page




CDB42448 pdf
CS42888
Figure 41.QSM Transition Band (Detail) ................................................................................................... 55
Figure 42.QSM Passband Ripple .............................................................................................................. 55
Figure 43.SSM Stopband Rejection .......................................................................................................... 56
Figure 44.SSM Transition Band ................................................................................................................ 56
Figure 45.SSM Transition Band (detail) .................................................................................................... 56
Figure 46.SSM Passband Ripple .............................................................................................................. 56
Figure 47.DSM Stopband Rejection .......................................................................................................... 56
Figure 48.DSM Transition Band ................................................................................................................ 56
Figure 49.DSM Transition Band (detail) .................................................................................................... 57
Figure 50.DSM Passband Ripple .............................................................................................................. 57
Figure 51.QSM Stopband Rejection ......................................................................................................... 57
Figure 52.QSM Transition Band ................................................................................................................ 57
Figure 53.QSM Transition Band (detail) .................................................................................................... 57
Figure 54.QSM Passband Ripple .............................................................................................................. 57
LIST OF TABLES
Table 1. I/O Power Rails ............................................................................................................................. 8
Table 2. Single-Speed Mode Common Frequencies ................................................................................ 29
Table 3. Double-Speed Mode Common Frequencies ............................................................................... 29
Table 4. Quad-Speed Mode Common Frequencies ................................................................................. 29
Table 5. I²S, LJ, RJ Clock Ratios .............................................................................................................. 30
Table 6. OLM#1 Clock Ratios ................................................................................................................... 30
Table 7. OLM#2 Clock Ratios ................................................................................................................... 30
Table 8. TDM Clock Ratios ....................................................................................................................... 30
Table 9. Serial Audio Interface Channel Allocations ................................................................................. 33
Table 10. MCLK Frequency Settings for I²S, Left and Right Justified Interface Formats .......................... 42
Table 12. DAC Digital Interface Formats .................................................................................................. 43
Table 11. MCLK Frequency Settings for TDM & OLM Interface Formats ................................................. 43
Table 13. ADC Digital Interface Formats .................................................................................................. 44
Table 14. Example AOUT Volume Settings .............................................................................................. 47
Table 15. Example AIN Volume Settings .................................................................................................. 48
DS717F1
5

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CDB42448 arduino
CS42888
ANALOG INPUT CHARACTERISTICS (COMMERCIAL)
(Test Conditions (unless otherwise specified): TA = -10 to +70°C; VD = VLS = VLC = 3.3 V±5%, VA = 5 V±5%;
Full-scale input sine wave: 1 kHz through the active input filter in Figure 25 on page 51 and Figure 26 on page 51;
Measurement Bandwidth is 10 Hz to 20 kHz.)
Differential
Single-Ended
Parameter
Min Typ Max Min Typ Max Unit
Fs=48 kHz, 96 kHz, 192 kHz
Dynamic Range
A-weighted
unweighted
40 kHz bandwidth unweighted
99
96
-
105
102
99
-
-
-
96 102
93 99
96
-
-
-
dB
dB
dB
Total Harmonic Distortion + Noise -1 dB - -98 -92 - -95 -89 dB
(Note 5)
-20 dB - -82 -
- -79 - dB
-60 dB - -42 -
- -39 - dB
40 kHz bandwidth -1 dB - -90 -
- -90 - dB
ADC1-2 Interchannel Isolation
- 90 -
- 90 - dB
DC Accuracy
Interchannel Gain Mismatch
- 0.1 -
- 0.1 - dB
Gain Drift
- ±100 -
- ±100 - ppm/°C
Analog Input
Full-Scale Input Voltage
1.06*VA 1.12*VA 1.18*VA 0.53*VA 0.56*VA 0.59*VA Vpp
Differential Input Impedance (Note 6)
18 - - - - - kΩ
Single-Ended Input Impedance (Note 7) - - - 18 - - kΩ
Common Mode Rejection Ratio (CMRR) - 82 - - - - dB
DS717F1
11

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