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CDB5343 Schematic ( PDF Datasheet ) - Cirrus Logic

Teilenummer CDB5343
Beschreibung Evaluation Board
Hersteller Cirrus Logic
Logo Cirrus Logic Logo 




Gesamt 23 Seiten
CDB5343 Datasheet, Funktion
www.DataSheet4U.com
CDB5343
CDB5343: Evaluation Board for CS5343
Features
Description
 Demonstrates Recommended Layout and
Grounding Arrangements
 CS8406 Generates S/PDIF and EIAJ-340-
Compatible Digital Audio
 Requires Only an Analog Signal Source
and Power Supply for a Complete Analog-
to-Digital Converter System
The CDB5343 evaluation board is an excellent
means for quickly evaluating the CS5343 24-
bit, stereo A/D converter. Evaluation requires
a digital signal analyzer, an analog source,
and a power supply.
Also included is an CS8406 digital audio inter-
face transmitter that generates S/PDIF and
EIAJ-340-compatible audio data. The digital
audio data is available via RCA phone and op-
tical connectors.
ANALOG
INPUT
CS5343
98 dB, 96 kHz, Audio A/D
Converter
CS8406
AES/EBU
S/PDIF
TRANSMITTER
S/PDIF
OUTPUT
I/O FOR
CLOCKS
AND DATA
http://www.cirrus.com
Copyright © Cirrus Logic, Inc. 2006
(All Rights Reserved)
AUGUST '06
DS687DB2






CDB5343 Datasheet, Funktion
CDB5343
8. CONNECTORS
Table 1 lists the connectors on the CDB5343, the reference designator of each connector, the directionality, and
the associated signal.
REFERENCE
CONNECTOR DESIGNATOR INPUT/OUTPUT
+5V J2 INPUT
GND J1 INPUT
AINR J7 INPUT
AINL J5 INPUT
Co-axial
J6
OUTPUT
Optical J9 OUTPUT
I/O HDR
J3 INPUT/OUTPUT
SIGNAL
+5 V power to crystal oscillator and DC voltage regulator
Ground connection from the power supply
Analog input right channel
Analog input left channel
Digital audio (S/PDIF) output
Digital audio (S/PDIF) output
Master Clock, Serial Clock, Left/Right Clock, SDOUT
Table 1. System Connections
9. JUMPER AND SWITCH SETTINGS
The user can fully configure the CDB5343 with a bank of six DIP switches (S1) and a single jumper setting on header
J4.
9.1 Jumper J4
This jumper selects the magnitude of VA, either 3.3 V or 5 V. The CS5343 is a single-supply device; there-
fore the magnitude of VA affects the full-scale analog input voltage as well as the digital I/O voltage. Digital
I/O is always fixed at VA, and the full-scale input is nominally 0.56xVA Vpp, as specified in the CS5343 data
sheet. If the user selects 5 V, the CS5343 full-scale analog input voltage is 2.82 Vpp (1 Vrms) and the digital
I/O is set to 5 V. If 3.3 V is selected, the full-scale analog input voltage is 1.86 Vpp (660 mVrms) and digital
I/O is 3.3 V.
9.2 Switch S1
Table 2 shows the available settings for S1 with the default settings.
CS5343
CS8406
MCLK
SCLK, LRCK
SPEED
MCLK/LRCK
OPEN
MASTER (default)
MASTER
FROM HDR
FROM HDR
DSM
256x (default)
CLOSED
SLAVE
SLAVE (default)
TO HDR (default)
TO HDR (default)
SSM (default)
384x
Table 2. CDB5343 S1 Settings
9.2.1
CS5343
This switch configures the CS5343 for either Master Mode or Slave Mode operation. When set as clock
Master, the CS8406 must be set to “Slave” and “SCLK, LRCK” must be set to “TO HDR.” When CS5343
is configured for Slave Mode, the CS8406 must be set for Master Mode, or “SCLK, LRCK” must be set to
“FROM HDR.”
6 DS687DB2

6 Page









CDB5343 pdf, datenblatt
13.CDB PERFORMANCE CURVES
13.1 Total Harmonic Distortion + Noise (THD+N)
Figure 17 shows typical THD+N performance of the CS5343 installed on the CDB5343. Performance curves are displayed for each channel
with the CS5343 running at Single-Speed in both Master and Slave Modes and for VA voltages of both +3.3 V and 5 V.
+0T
-5
-10
-15
-20
-25
-30
-35
-40
d -45
B
F
-50
S -55
-60
-65
-70
-75
-80
-85
-90
-95
-100
CDB5343 (Rev A device) THD+N vs. Frequency
+0
-5
-10
-15
-20
-25
-30
-35
-40
-45 d
-50
B
F
-55 S
-60
-65
-70
-75
-80
-85
-90
-95
-100
2k 4k 6k 8k 10k 12k 14k 16k 18k 20k
Hz
Sweep Trace Color Line Style Thick Data
Axis Comment
1
1
Blue
Solid
1 DSP Anlr.THD+N Ampl A Left 5V Master SSM 256x
1
2
Blue
Solid
1 DSP Anlr.THD+N Ampl B Right 5V Master SSM 256x
2
1
Red
Solid
1 DSP Anlr.THD+N Ampl A Left 5V Slave SSM 256x
2
2
Red
Solid
1 DSP Anlr.THD+N Ampl B Right 5V Slave SSM 256x
3 1 Green Solid 1 DSP Anlr.THD+N Ampl A Left 3.3 V Slave SSM 256x
3 2 Green Solid 1 DSP Anlr.THD+N Ampl B Right 3.3 V Slave SSM 256x
4 1 Yellow Solid 1 DSP Anlr.THD+N Ampl A Left 3.3 V Slave SSM 256x
4 2 Yellow Solid 1 DSP Anlr.THD+N Ampl B Right 3.3 V Slave SSM 256x
Figure 17. CDB5343 THD+N Performance

12 Page





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