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Teilenummer | CDB5334 |
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Beschreibung | (CDB5334 - CDB5360) Evaluation Board | |
Hersteller | Cirrus Logic | |
Logo | ||
Gesamt 18 Seiten www.DataSheet4U.com
CDB5334/35/60
Evaluation Board for CS5334/CS5335/CS5360
Features
l Demonstrates recommended layout and
grounding arrangements
l CS8402A Generates AES/EBU, S/PDIF, &
EIAJ-340 Compatible Digital Audio
l Buffered Serial Output Interface
l Digital and Analog Patch Areas
l On-board or externally supplied system
timing
I
Description
The CDB5334/35/60 evaluation board is an excellent
means for quickly evaluating the CS5334, CS5335, or
CS5360 stereo A/D converters. Evaluation requires a
digital signal processor, a low distortion analog signal
source and a power supply. Analog inputs are provided
via XLR connectors for both channels.
Also included is a CS8402A digital audio interface trans-
mitter which generates AES/EBU, S/PDIF, and EIAJ-340
compatible audio data. The digital audio data is available
via RCA phono, and optical connectors.
The evaluation board may also be configured to accept
external timing signals for operation in a user application
during system development.
ORDERING INFO
CDB5334/35/60
Preliminary Product Information
Cirrus Logic, Inc.
Crystal Semiconductor Products Division
P.O. Box 17847, Austin, Texas 78760
(512) 445 7222 FAX: (512) 445 7581
http://www.crystal.com
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
Copyright © Cirrus Logic, Inc. 1997
(All Rights Reserved)
OCT ‘97
DS194DB3
1
CDB5334/35/60
Switch # 0 = closed, 1 = open
Comment
8, 7 MCLK_S1, MCLK_S0 Divides MCLK_5335 to generate MCLK_8402 for the CS8402A trnsmitter
*0 0 Generates a 128x Fs clock when using a 256x Fs oscillator
0 1 RESERVED
1 0 Generates a 128x Fs clock when using a 384x Fs oscillator
1 1 Generates a 128x Fs clock when using a 512x Fs oscillator
6, 5 *0 0 RESERVED
4, 3
DIF1, DIF0
Selects the digital interface format for the CS5334/35/60, and CS8402A
*0 0 Configures the CS5334/35/60 for Format 0, and the CS8402A for Format 1
0 1 Configures the CS5334/35/60 for Format 1, and the CS8402A for Format 1
1 0 Configures the CS5334/35/60 for Format 2 (I2S), and the CS8402A for Format 4
(I2S)
1 1 Places the CS5334/35/60 in power down mode
2, 1 PU_S1, PU_S0 Adjusts the frequency of the Peak Update signal for PSL bits
*0 0 Updates the PSL bits at a frequency of LRCK/211
0 1 Updates the PSL bits at a frequency of LRCK/213
1 0 Updates the PSL bits at a frequency of LRCK/215
1 1 Updates the PSL bits at a frequency of LRCK/217
Table 3. Switch Definitions
Switch # 0 = closed, 1 = open
Comment
6
PRO = 0
Consumer Mode (C0 = 0)
8, 5
FC1, FC0
C24, C25, C26, C27 - Sample Frequency
0 0 0000 - 44.1 kHz
*0 1 0100 - 48 kHz
1 0 1100 - 32 kHz
1 1 0000 - 44.1 kHz, CD Mode
7 C3 C3, C4, C5 - Emphasis (1 of 8 bits)
*1 000 - None
0 100 - 50/15 µs
4 C2 C2 - Copy/Copyright
*1 0 - Copy Inhibited /Copyright Assered
0 1 - Copy Permitted/Copyright Not Asserted
3 C15 C15 - Generates Status
*1 0 - Definition is based on category code
0 1 - See CS8402A Data Sheet, App. A
1, 2
C8, C9
C8 - C14 - Category Code (2 of 7 bits)
1 1 0000000 - General
1 0 0100000 - PCM encoder/decoder
0 1 1000000 - Compact Disk - CD
*0 0 1100000 - Digital Audio Tape - DAT
* Default setting from factory
Table 4. CS8402A Switch Definitions - Consumer Mode
6 DS194DB3
6 Page CDB5334/35/60
Figure 6. I/O Interface for Clocks and Data
Figure 7. Decoupling Caps for PLD
12 DS194DB3
12 Page | ||
Seiten | Gesamt 18 Seiten | |
PDF Download | [ CDB5334 Schematic.PDF ] |
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