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PDF CDB6422 Data sheet ( Hoja de datos )
| Número de pieza | CDB6422 | |
| Descripción | Enhanced Full-Duplex Speakerphone IC | |
| Fabricantes | Cirrus Logic | |
| Logotipo |  |
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CS6422
CS6422
EEnnhhaanncceeddFFuulll--Dduupplleexx SSppeeaakkeerrpphhoonnee IICC
Features
l Single-chip, full-duplex, hands-free operation
l Optional Tx Noise Guard
l Programmable attenuation during double-talk
l Optional 34 dB microphone preamplifier
l Dual channel AGC’ed volume controls with
mute
l Dual integrated 80 dB IDR codecs
l Speech-trained Network and Acoustic Echo
Cancellers
l Rx and Tx supplementary echo suppression
l Configurable half-duplex training mode
l Powerdown mode
l Microcontroller Interface
General Description
Most modern speakerphones use half-duplex operation,
which alternates transmission between the far-end talker
and the speakerphone user. This is done to ensure sta-
bility because the acoustic coupling between the
speaker and microphone is much higher in speaker-
phones than in handsets where the coupling is
mechanically suppressed.
The CS6422 enables full-duplex conversation using
echo cancellation and suppression in a single-chip solu-
tion. The CS6422 can easily replace existing half-duplex
speakerphone ICs with a huge increase in conversation
quality.
The CS6422 consists of telephone & audio interfaces,
two codecs and an echo-cancelling DSP.
ORDERING INFORMATION
See page 48.
CS6422-IS -40o to 85oC 20-pin SOIC
CDB6422 Evaluation Board
NC1 NC2 NC3 NC4
DVDD
AVDD
NI 17
RGain
9
ADC
(0, 6, 9.5, 12 dB)
Network
Sidetone
(none, -24, NSdt
-18, -12 dB)
NO 4
DAC
10 11 12
16
RVol
+
Σ
+-
Rx
Suppression
(Mute, -12 to +30 dB)
Pre-emphasis
Network
Filter
Echo
Canceller
Pre-emphasis
Filter
Tx
Suppression
Acoustic
Echo
Canceller
TVol - +
Σ+
1
DAC
Acoustic
ASdt Sidetone
(none, -24,
-18, -12 dB)
ADC
TGain
3
AO
Clock
Generation
14
CLKI
13
CLKO
Mic
20
API
34 dB
1 kΩ
18
APO
Microcontroller Interface
(Mute, -12 to +30 dB)
(0, 6, 9.5, 12 dB)
Voltage
Reference
8765
15
2
19
Preliminary Product Information
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
Pht.tOp:.//Bwowxw1.7c8ir4ru7s,.Acoumstin, Texas 78760
(512) 445 7222 FAX: (512) 445 7581
http://www.cirrus.com
Copyright © CirrCuospLyorgigich,t IncC. i2rr0u0s5Logic, Inc. 2001
(All Rights Rese(rAvelldR)ights Reserved)
SJUEPL ‘‘0015
DSD2S9259P5PF41
1
1 page  
CS6422
1. CHARACTERISTICS AND SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
Parameter
DC Supply (AVDD, DVDD)
Input Current (Except supply pins)
Input Voltage
Ambient Operating Temperature
Storage Temperature
Symbol
Analog
Digital
Iin
Vina
Vind
TA
Tstg
Min
-0.3
-10
-0.3
-0.3
-40
-65
Max
6.0
+10
AVDD+0.3
DVDD+0.3
85
150
Units
V
mA
V
°C
°C
WARNING: Operation beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
Parameter
DC Supply (AVDD, DVDD)
Ambient Operating Temperature
Symbol Min Typ Max Units
4.5 5.0 5.5
V
Commercial TAOp
0
25 70 °C
Industrial
-40 25
85
POWER CONSUMPTION (TA = 25°C, DVDD = AVDD = 5 V, fXTAL = 20.480 MHz) (Note 1)
Parameter
Power Supply Current, Analog (RST=0)
Power Supply Current, Analog (RST=1)
Power Supply Current, Digital (RST=0)
Power Supply Current, Digital (RST=1)
Symbol Min Typ Max
PDA0
1
PDA 10 20
PDD0
1
PDD 50 80
Notes: 1. AO and NO outputs are not loaded.
ANALOG CHARACTERISTICS (TA = 25°C, DVDD = AVDD = 5 V, fXTAL = 20.480 MHz)
Parameter
Symbol Min Typ Max
Input Offset Voltage (APO, NI)
2.12
Output Offset Voltage (AO, NO)
2.12
Transmit Group Delay
(Note 2)
6
Receive Group Delay
Input Impedance (APO, NI)
Load Impedance (AO, NO)
Power Supply Rejection (1 kHz)
(Note 2)
Zin
Zload
10
1.5
40
6
Units
mA
mA
mA
mA
Units
V
V
ms
ms
MΩ
kΩ
dB
Notes: 2. These parameters are guaranteed by design or by characterization.
DS295F1
5
5 Page 
CS6422
Receive Path
NI 17 RGain
ADC
(0,6,9.5,12 dB)
FAR-END
NO 4
DAC
DAC
3 AO
D
S
P
ADC
TGain
Mic 1kΩ
NEAR-END
34 dB 20 API
(0,6,9.5,12 dB)
CS6422
Voltage
Reference
18 19
Transmit Path
APO
MB
Figure 6. Analog Interface
of higher amplitude will clip the ADC input and
will result in poor echo canceller performance. See
Section 4., “Design Considerations” for more de-
tails.
The outputs are delta-sigma digital to analog con-
verters (DACs) and have similar requirements to
the ADCs. The DACs are pre-compensated to ex-
pect a single-pole RC filter with a corner frequency
at 4 kHz. The full scale voltage output from a DAC
is 1.1 Vrms (3.1 Vpp) maximum, 1 Vrms typical, bi-
ased around 2.12 VDC.
3.1.1 Acoustic Interface
The pins API (pin 20), APO (pin 18), AO (pin 3),
and MB (pin 19) form the Acoustic Interface. A
block diagram of the Acoustic Interface is shown in
Figure 6.
API and APO are, respectively, the input and out-
put of the built-in microphone pre-amplifier. The
pre-amplifier is an inverting amplifier with a fixed
gain of 34 dB biased around an input offset voltage
of 2.12 V. APO is the output of the pre-amplifier
after a 1 kΩ (typical) resistor. The circuitry con-
nected to the amplifier input must present low
source impedance (<100 Ω) to the API pin or the
gain will be reduced. When using the internal mic
preamp, a 0.022 µF capacitor should be placed be-
tween APO and ground to provide the anti-aliasing
filter required by the ADC, as shown in Figure 4.
The pre-amplifier may be bypassed by clearing the
‘Mic’ bit (Register 0, bit 15) using the Microcontrol-
ler Interface (see Section 3.2, “Microcontroller Inter-
face”). If the internal mic preamp is not used, a
0.022 µF capacitor should be tied between API and
ground, and APO should be driven directly. In this
case, the signal into APO must be low-pass filtered
by a single-pole RC filter with a corner frequency at
8 kHz (see Figure 5).
Following the pre-amplifier is a programmable an-
alog gain stage, called TGain, which is controlled
DS295F1
11
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| PDF Descargar | [ Datasheet CDB6422.PDF ] | |
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