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PDF CDB5342 Data sheet ( Hoja de datos )
| Número de pieza | CDB5342 | |
| Descripción | MULTI-BIT AUDIO A/D CONVERTER | |
| Fabricantes | Cirrus Logic | |
| Logotipo |  |
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CS5342
105 dB, 192 kHz, Multi-bit Audio A/D Converter
Features
Advanced Multi-bit Delta-Sigma Architecture
24-bit Conversion
Supports all audio sample rates including
192 kHz.
105 dB Dynamic Range at 5 V
-98 dB THD+N
High-pass Filter to Remove DC Offsets
Analog/Digital Core Supplies From 3.3 V to 5 V
Supports logic levels between 2.5 V and 5 V.
Low-latency Digital Filter
Automatic Mode Selection
Supports 384x MCLK/LRCK Ratios.
General Description
The CS5342 is a complete analog-to-digital converter for
digital audio systems. It performs sampling, analog-to-
digital conversion and anti-alias filtering, generating
24-bit values for both left and right inputs in serial form at
sample rates up to 200 kHz per channel.
The CS5342 uses a 5th-order, multi-bit Delta-Sigma
modulator followed by digital filtering and decimation,
which removes the need for an external anti-alias filter.
The CS5342 is ideal for audio systems requiring wide dy-
namic range, negligible distortion and low noise, such as
set-top boxes, DVD-karaoke players, DVD recorders,
A/V receivers, and automotive applications.
ORDERING INFORMATION
CS5342-CZZ Lead-free -10° to 70° C
CS5342-DZZ Lead-free -40° to 85° C
CDB5342
16-pin TSSOP
16-pin TSSOP
Evaluation Board
VQ REFGND
VL
2.5V - 5.0V SCLK LRCK SDOUT MCLK
FILT+
Voltage Reference
Serial Output Interface
AINL
+
-
S/H
AINR
+
-
S/H
LP Filter
DAC
LP Filter
DAC
VA
3.3V - 5.0V
Q
Digital
Decimation
High
Pass
Filter
Filter
Q
Digital
Decimation
High
Pass
Filter
Filter
GND
VD
3.3V - 5.0V
RST
M0
M1
Preliminary Product Information
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
www.cirrus.com
©Copyright Cirrus Logic, Inc. 2004
(All Rights Reserved)
AUG ‘04
DS608PP2
1 page  
CS5342
ANALOG CHARACTERISTICS (CS5342-CZZ) Test conditions (unless otherwise specified):
Input test signal is a 1 kHz sine wave; measurement bandwidth is 10 Hz to 20 kHz.
Parameter
Symbol Min Typ Max Unit
VA = 3.3 V
Single Speed Mode
Fs = 48 kHz
Dynamic Range
A-weighted
unweighted
96 102
93 99
- dB
- dB
Total Harmonic Distortion + Noise
(Note 6)
-1 dB
-20 dB
-60 dB
THD+N
-
-
-
-95 -89 dB
-79 - dB
-39 - dB
Double Speed Mode
Fs = 96 kHz
Dynamic Range
A-weighted
unweighted
40 kHz bandwidth unweighted
96 102
93 99
- 96
- dB
- dB
- dB
Total Harmonic Distortion + Noise
40 kHz bandwidth
(Note 6)
-1 dB
-20 dB
-60 dB
-1 dB
THD+N
-
-
-
-
-95 -89 dB
-79 - dB
-39 - dB
-87 - dB
Quad Speed Mode (Note 2) Fs = 192 kHz
Dynamic Range
A-weighted
unweighted
40 kHz bandwidth unweighted
96 102
93 99
- 96
- dB
- dB
- dB
Total Harmonic Distortion + Noise
40 kHz bandwidth
(Note 6)
-1 dB
-20 dB
-60 dB
-1 dB
THD+N
-
-
-
-
-95 -89 dB
-79 - dB
-39 - dB
-87 - dB
VA = 5.0 V
Single Speed Mode
Fs = 48 kHz
Dynamic Range
A-weighted
unweighted
99 105
96 102
- dB
- dB
Total Harmonic Distortion + Noise
(Note 6)
-1 dB
-20 dB
-60 dB
THD+N
-
-
-
-98 -92 dB
-82 - dB
-42 - dB
Double Speed Mode
Fs = 96 kHz
Dynamic Range
A-weighted
unweighted
40 kHz bandwidth unweighted
99 105
96 102
- 99
- dB
- dB
- dB
Total Harmonic Distortion + Noise
40 kHz bandwidth
(Note 6)
-1 dB
-20 dB
-60 dB
-1 dB
THD+N
-
-
-
-
-98 -92 dB
-82 - dB
-42 - dB
-95 - dB
DS608PP2
5
5 Page 
CS5342
SWITCHING CHARACTERISTICS - SERIAL AUDIO PORT (Logic "0" = GND = 0 V;
Logic "1" = VL, CL = 20 pF)
Parameter
MCLK Specifications
MCLK Period
MCLK Pulse Duty Cycle
Master Mode
SCLK falling to LRCK
SCLK falling to SDOUT valid
SCLK Duty Cycle
Slave Mode
Single Speed*
LRCK Duty Cycle
SCLK Period
SCLK Duty Cycle
SDOUT valid before SCLK rising
SDOUT valid after SCLK rising
SCLK falling to LRCK edge
Double Speed*
LRCK Duty Cycle
SCLK Period (Note 9)
SCLK Duty Cycle
SDOUT valid before SCLK rising
SDOUT valid after SCLK rising
SCLK falling to LRCK edge
Quad Speed* (Note 2)
LRCK Duty Cycle
SCLK Period (Note 9)
SCLK Duty Cycle
SDOUT valid before SCLK rising
SDOUT valid after SCLK rising
SCLK falling to LRCK edge
Symbol
tclkw
Single-Speed
Double-Speed
Quad-Speed
tmslr
tsdo
Min
26
52
40
-20
-
-
-
-
Typ Max Unit
- 31 ns
-
1303
ns
- 60 %
- 20 ns
- 32 ns
50 - %
50 - %
33 - %
tsclkw
tstp
thld
tslrd
tsclkw
tstp
thld
tslrd
tsclkw
tstp
thld
tslrd
40
290
45
10
5
-20
40
193
45
10
5
-20
40
104
40
10
5
-8
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
60 %
- ns
55 %
- ns
- ns
20 ns
60 %
- ns
55 %
- ns
- ns
20 ns
60 %
- ns
50 %
- ns
- ns
8 ns
* For a description of Speed Modes, please refer to Table 1 on page 15
Notes: 9. SCLK must be derived synchronously from MCLK and the ratio of SCLK/LRCK must be equal to 48.
DS608PP2
11
11 Page | ||
| Páginas | Total 22 Páginas | |
| PDF Descargar | [ Datasheet CDB5342.PDF ] | |
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