|
|
Teilenummer | CDB43L21 |
|
Beschreibung | Stereo Digital to Analog Converter | |
Hersteller | Cirrus Logic | |
Logo | ||
Gesamt 30 Seiten www.DataSheet4U.com
CS43L21
Low Power, Stereo Digital to Analog Converter
FEATURES
98 dB Dynamic Range (A-wtd)
-86 dB THD+N
Headphone Amplifier - GND Centered
– On-Chip Charge Pump Provides -VA_HP
– No DC-Blocking Capacitor Required
– 46 mW Power Into Stereo 16 Ω @ 1.8 V
– 88 mW Power Into Stereo 16 Ω @ 2.5 V
– -75 dB THD+N
Digital Signal Processing Engine
– Bass & Treble Tone Control, De-Emphasis
– PCM Mix w/Independent Vol Control
– Master Digital Volume Control and Limiter
– Soft Ramp & Zero Cross Transitions
Beep Generator
– Tone Selections Across Two Octaves
– Separate Volume Control
– Programmable On & Off Time Intervals
– Continuous, Periodic or One-Shot Beep
Selections
Programmable Peak-Detect and Limiter
Pop and Click Suppression
SYSTEM FEATURES
24-bit Conversion
4 kHz to 96 kHz Sample Rate
Multi-bit Delta Sigma Architecture
Low Power Operation
– Stereo Playback: 12.93 mW @ 1.8 V
Variable Power Supplies
– 1.8 V to 2.5 V Digital & Analog
– 1.8 V to 3.3 V Interface Logic
Power Down Management
Software Mode (I²C® & SPI™ Control)
Hardware Mode (Stand-Alone Control)
Digital Routing/Mixes:
– Mono Mixes
Flexible Clocking Options
– Master or Slave Operation
– High-Impedance Digital Output Option (for
easy MUXing between DAC and Other
Data Sources)
– Quarter-Speed Mode - (i.e. Allows 8 kHz Fs
while maintaining a flat noise floor up to
16 kHz)
1.8 V to 3.3 V
1.8 V to 2.5 V
1.8 V to 2.5 V
Serial Audio
Input
Hardware
Mode or I2C &
SPI Software
Mode
Control Data
Reset
Beep
Generator
Register
Configuration
Digital
Signal
Processing
Engine
MUX
Switched
Capacitor DAC
Multibit
and Filter
∆Σ Modulator
Switched
Capacitor DAC
MUX
and Filter
Headphone
Amp - GND
Centered
Headphone
Amp - GND
Centered
Charge
Pump
Left HP Out
Right HP Out
Advance Product Information
http://www.cirrus.com
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
Copyright © Cirrus Logic, Inc. 2006
(All Rights Reserved)
JULY '06
DS723A1
1. PIN DESCRIPTIONS - SOFTWARE (HARDWARE) MODE
CS43L21
32 31 30 29 28 27 26 25
LRCK 1
SDA/CDIN (MCLKDIV2) 2
SCL/CCLK (I²S/LJ) 3
ADO/CS (DEM) 4
VA_HP 5
FLYP 6
GND_HP 7
FLYN 8
CS43L21
24 TSTO
23 TSTO
22 TSTO
21 TSTO
20 TSTO
19 TSTO
18 TSTO
17 TSTO
9 10 11 12 13 14 15 16
Pin Name
LRCK
SDA/CDIN
(MCLKDIV2)
SCL/CCLK
(I²S/LJ)
AD0/CS
(DEM)
VA_HP
FLYP
GND_HP
FLYN
VSS_HP
# Pin Description
1 Left Right Clock (Input/Output) - Determines which channel, Left or Right, is currently active on the
serial audio data line.
Serial Control Data (Input/Output) - SDA is a data I/O in I²C Mode. CDIN is the input data line for the
2 control port interface in SPI Mode.
MCLK Divide by 2 (Input) - Hardware Mode: Divides the MCLK by 2 prior to all internal circuitry.
Serial Control Port Clock (Input) - Serial clock for the serial control port.
3 Interface Format Selection (Input) - Hardware Mode: Selects between I²S & Left-Justified interface for-
mats for the DAC.
Address Bit 0 (I²C) / Control Port Chip Select (SPI) (Input) - AD0 is a chip address pin in I²C Mode; CS
4 is the chip-select signal for SPI format.
De-Emphasis (Input) - Hardware Mode: Enables/disables the de-emphasis filter.
5 Analog Power For Headphone (Input) - Positive power for the internal analog headphone section.
6 Charge Pump Cap Positive Node (Input) - Positive node for the external charge pump capacitor.
7 Analog Ground (Input) - Ground reference for the internal headphone/charge pump section.
8 Charge Pump Cap Negative Node (Input) - Negative node for the external charge pump capacitor.
9 Negative Voltage From Charge Pump (Output) - Negative voltage rail for the internal analog head-
phone section.
6 DS723A1
6 Page CS43L21
ANALOG OUTPUT CHARACTERISTICS (COMMERCIAL - CNZ)
(Test conditions (unless otherwise specified): Input test signal is a full-scale 997 Hz sine wave; measurement
bandwidth is 10 Hz to 20 kHz; Sample Frequency = 48 kHz; test load RL = 10 kΩ, CL = 10 pF for the line output
(see Figure 3), and test load RL = 16 Ω, CL = 10 pF (see Figure 3) for the headphone output. HP_GAIN[2:0] = 011.)
Parameter (Note 4)
RL = 10 kΩ
Dynamic Range
18 to 24-Bit
16-Bit
A-weighted
unweighted
A-weighted
unweighted
Total Harmonic Distortion + Noise
18 to 24-Bit
16-Bit
RL = 16 Ω
0 dB
-20 dB
-60 dB
0 dB
-20 dB
-60 dB
Dynamic Range
18 to 24-Bit
16-Bit
A-weighted
unweighted
A-weighted
unweighted
Total Harmonic Distortion + Noise
18 to 24-Bit
0 dB
-20 dB
-60 dB
16-Bit
0 dB
-20 dB
-60 dB
Other Characteristics for RL = 16 Ω or 10 kΩ
Output Parameters
(Note 5)
Modulation Index (MI)
Analog Gain Multiplier (G)
Full-scale Output Voltage (2•G•MI•VA) (Note 5)
Full-scale Output Power (Note 5)
Interchannel Isolation (1 kHz)
Interchannel Gain Mismatch
Gain Drift
AC-Load Resistance (RL)
Load Capacitance (CL)
16 Ω
10 kΩ
(Note 6)
(Note 6)
VA = 2.5V (nominal)
VA = 1.8V (nominal)
Min Typ Max Min Typ Max
92 98
-
89 95
-
89 95
-
86 92
-
- 96 - - 93 -
- 93 - - 90 -
- -86 -78 - -88 -82
- -75 -
- -72 -
- -35 -
- -32 -
- -86 -
- -88 -
- -73 -
- -70 -
- -33 -
- -30 -
92 98
-
89 95
-
89 95
-
86 92
-
- 96 - - 93 -
- 93 - - 90 -
- -75 -69 - -75 -69
- -75 -
- -72 -
- -35 -
- -32 -
- -75 -
- -75 -
- -73 -
- -70 -
- -33 -
- -30 -
-
0.6787
0.6047
-
-
0.6787
0.6047
-
Refer to Table “Line Output Voltage Characteristics” on
page 14
Refer to Table “Headphone Output Power Characteristics”
on page 15
- 80 - - 80 -
- 95 - - 93 -
-
0.1 0.25
-
0.1 0.25
- ±100 -
- ±100 -
16 -
- 16 -
-
-
- 150 -
- 150
Unit
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
Vpp
mW
dB
dB
dB
ppm/°
C
Ω
pF
12 DS723A1
12 Page | ||
Seiten | Gesamt 30 Seiten | |
PDF Download | [ CDB43L21 Schematic.PDF ] |
Teilenummer | Beschreibung | Hersteller |
CDB43L21 | Stereo Digital to Analog Converter | Cirrus Logic |
Teilenummer | Beschreibung | Hersteller |
CD40175BC | Hex D-Type Flip-Flop / Quad D-Type Flip-Flop. |
Fairchild Semiconductor |
KTD1146 | EPITAXIAL PLANAR NPN TRANSISTOR. |
KEC |
www.Datenblatt-PDF.com | 2020 | Kontakt | Suche |