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CDB4352 Schematic ( PDF Datasheet ) - Cirrus Logic

Teilenummer CDB4352
Beschreibung Evaluation Board
Hersteller Cirrus Logic
Logo Cirrus Logic Logo 




Gesamt 21 Seiten
CDB4352 Datasheet, Funktion
www.DataSheet4U.com
CDB4352
Evaluation Board for CS4352
Features
 Demonstrates Recommended Layout And
Grounding Arrangements
 CS8416 Receives S/PDIF, & EIAJ-340-
Compatible Digital Audio
 Headers for External PCM Audio
 Requires Only a Digital Signal Source and
Power Supplies for a Complete Digital-to-
Analog Converter System
Description
The CDB4352 evaluation board is an excellent means
for quickly evaluating the CS4352 24-bit, high-perfor-
mance stereo D/A converter. Evaluation requires an
analog signal analyzer, a digital signal source, and a
power supply. Analog line-level outputs are provided via
RCA phono jacks.
The CS8416 digital audio receiver IC provides the sys-
tem timing necessary to operate the Digital-to-Analog
converter and will accept S/PDIF and EIAJ-340-com-
patible audio data. The evaluation board may also be
configured to accept external timing and data signals for
operation in a user application during system
development.
ORDERING INFORMATION
CDB4352
Evaluation Board
Hardware Switches
Clocks/Data
Header
S/PDIF Input
(CS8416)
Reset
Mux
CS4352
Reset
Analog Output
(Line Level)
Muting
http://www.cirrus.com
Copyright © Cirrus Logic, Inc. 2006
(All Rights Reserved)
SEPTEMBER '06
DS684DB1






CDB4352 Datasheet, Funktion
9. PERFORMANCE PLOTS
CDB4352
+0
-10
-20
-30
-40
-50
d -60
B
r -70
A -80
-90
-100
-110
-120
-130
-140
20
50 100 200
500 1k
2k
5k
Hz
Figure 1. FFT (48 kHz, 0 dB)
10k 20k
+0
-10
-20
-30
-40
-50
d -60
B
r -70
A -80
-90
-100
-110
-120
-130
-140
20
50 100 200
500 1k
2k
5k
Hz
Figure 2. FFT (48 kHz, -60 dB)
10k 20k
+0
-10
-20
-30
-40
-50
d -60
B
r -70
A -80
-90
-100
-110
-120
-130
-140
20
50 100 200
500 1k
2k
5k
Hz
Figure 3. FFT (48 kHz, No Input)
10k 20k
+0
-10
-20
-30
-40
-50
d -60
B
r -70
A -80
-90
-100
-110
-120
-130
-140
20k
40k
60k
80k
100k
120k
Hz
Figure 4. FFT (48 kHz Out-of-Band, No Input)
+0
-10
-20
-30
-40
d
B -50
r
-60
A
-70
-80
-90
-100
-110
20
50 100 200
500 1k
2k
5k 10k
Hz
Figure 5. 48 kHz, THD+N vs. Input Freq
20k
+0
-10
-20
-30
-40
d
B -50
r
-60
A
-70
-80
-90
-100
-110
-120
-100 -80 -60 -40 -20
dBFS
Figure 6. 48 kHz, THD+N vs. Level
+0
6 DS684DB1

6 Page









CDB4352 pdf, datenblatt
11.SCHEMATICS
Reset
Circuit
8416 Digital
Audio Receiver
Figure 35
MCLK
SCLK
LRCK
SDIN
Hardware Switch Power
Figure 34
Figure 36
CS4352
Figure 32
Channel A
Outputs and Mute
Figure 33
Channel B
Outputs and Mute
Figure 33
PCM Inputs
Figure 34
Figure 31. System Block Diagram and Signal Flow

12 Page





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