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PDF C9851 Data sheet ( Hoja de datos )

Número de pieza C9851
Descripción Clock Generator
Fabricantes Cypress Semiconductor 
Logotipo Cypress Semiconductor Logotipo



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No Preview Available ! C9851 Hoja de datos, Descripción, Manual

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PRELIMINARY
C9851
Clock Generator for PentiumIII Server and Workstation Applications
Product Features
Six pairs of current referenced differential clocks
Two 3V 180° displaced Mref clocks for DRCG
One 66.6 MHz reference output
One 14.318 MHz reference output
Select logic for Differential Swing Control, Test
mode, Hi-Z, Power-down, Spread spectrum, and
limited frequency select
Cypress Spread Spectrum for EMI reduction
48 Pin SSOP Package
Frequency Selection Table
SEL 100/133 SELA SELB CPU(1:6), CPU#(1:6)
0 00
100 MHz
0 01
100 MHz
0 10
200 MHz
0 11
Hi-Z
1 0 0 133.3 MHz
1 01
25 MHz
1 10
200 MHz
1 11
REF/2
Block Diagram
Product Description
This device provides the necessary clocks for a
differential host bus system in multi-processor servers
and workstations. It also generates a 66.6MHz hub
clock for interfacing with a complimentary part, the
Cypress B9852. The 2 Mref clock outputs are 180
degrees out of phase and are used for interfacing with
the Direct Rambus Clock Generator (DRCG), C9820,
C9821, or C9822. This device integrates the Cypress
spread spectrum technology for optimum EMI
reduction.
3VMref,
3Vmref_b
50 MHz
Low
50 MHz
Hi-Z
66.67 MHz
50 MHz
66.7 MHz
REF/4
Table 1
3V66
66.67 MHz
Low
66.67 MHz
Hi-Z
66.67 MHz
66.67 MHz
66.67 MHz
REF
Pin Configuration
REF
14.318 MHz
Low
14.318 MHz
Hi-Z
14.318 MHz
14.318 MHz
14.318 MHz
REF
XIN OSC
XOUT
MultSel(0:1)
Spread#
SelA
SelB
SEL100/133
VCO
PwrDwn#
I
Control
VDDR
REF
VSSR
VDDA
I_Ref
VSSI
CPU (1:6)
CPU (1:6)#
VDDM
3VMRef
3VMRef_b
VSSM
VDDL
3V66
VSSL
VSSR
Ref
VDDR
XIN
XOUT
VSSR
VDDM
3VMref
3VMref_b
VSSM
VDD
VSS
VDDL
3V66
VSSL
SEL100/133
MultSel0
MultSel1
VDDA
VSSA
SelA
SelB
Spread#
PwrDwn#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48 VDD
47 VSS
46 VDDC
45 CPU1
44 CPU1#
43 VSSC
42 CPU2
41 CPU2#
40 VDDC
39 CPU3
38 CPU3#
37 VSSC
36 CPU4
35 CPU4#
34 VDDC
33 CPU5
32 CPU5#
31 VSSC
30 CPU6
29 CPU6#
28 VDDC
27 I_Ref
26 VSSA
25 VDDA
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07068 Rev. **
05/04/2001
Page 1 of 14

1 page




C9851 pdf
PRELIMINARY
C9851
Clock Generator for PentiumIII Server and Workstation Applications
Group Limits and Parameters (applicable to all settings: Sel133/100# = x) (Continued)
Output name
CPU[(1:6), (1:6)#]
3VMref, 3VMref_b
REF
3V66
Table 2.
Max Load
Rs = 33.2, Rp = 49.9
30 pF
20 pF
30 pF
Lumped Test Load Configurations
The following shows lumped test load configurations for the differential Host Clock Outputs.
(MULTsel1 = 0, MULTsel0 = 1)
Rs
33.2ohm
Rp
49.9ohm
Rs
33.2ohm
Rp
49.9ohm
Test Nodes
Fig.1A
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07068 Rev. **
05/04/2001
Page 5 of 14

5 Page





C9851 arduino
PRELIMINARY
C9851
Clock Generator for PentiumIII Server and Workstation Applications
Suggested Oscillator Crystal Parameters
Characteristic
Symbol
Min
Typ
Max Units Conditions
Frequency
Fo
14.17
14.31818
14.46
MHz
Tolerance
TC -
-
+/-100
PPM Note 1
Frequency Stability
TS
-
-
+/- 100
PPM Stability (TA -10 to +60C) Note 1
Operating Mode
--
-
-
Parallel Resonant, Note 1
Load Capacitance
CXTAL
-
20
- pF The crystal’s rated load. Note 1
Effective Series
Resistance (ESR)
RESR
-
40
- Ohms Note 2
Note1: For best performance and accurate frequencies from this device, It is recommended but not mandatory that the chosen
crystal meets or exceeds these specifications
Note 2: Larger values may cause this device to exhibit oscillator startup problems
To obtain the maximum accuracy, the total circuit loading capacitance should be equal to CXTAL. This loading capacitance is the
effective capacitance across the crystal pins and includes the clock generating device pin capacitance (CFTG), any circuit trace
capacitance (CPCB), and any onboard discrete load capacitance (CDISC).
The following formula and schematic illustrates the application of the loading specification of a crystal (CXTAL)for a design.
CL = (CXINPCB + CXINFTG + CXINDISC) X (CXOUTPCB + CXOUTFTG + CXOUTDISC)
(CXINPCB + CXINFTG + CXINDISC) + (CXOUTPCB + CXOUTFTG + COUTDISC)
Where:
CXTAL
CXOUTFTG
CXOUTFTG
CXINPCB
CXOUTPCB
CXINDISC
CXOUTDISC
= the load rating of the crystal
= the clock generators XIN pin effective device internal capacitance to ground
= the clock generators XOUT pin effective device internal capacitance to ground
= the effective capacitance to ground of the crystal to device PCB trace
= the effective capacitance to ground of the crystal to device PCB trace
= any discrete capacitance that is placed between the XIN pin and ground
= any discrete capacitance that is placed between the XOUT pin and ground
CXINPCB
CXINDISC
XIN
CXINFTG
CXOUTPCB
CXOUTDISC
XOUT CXOUTFTG
Clock Generator
As an example, and using this formula for this datasheet’s device, a design that has no discrete loading capacitors (CDISC) and each
of the crystal to device PCB traces has a capacitance (CPCB) to ground of 4pF (typical value) would calculate as:
CL = (4pF + 36pF + 0pF) X (4pF + 36pF + 0pF) = 40 X 40 = 1600 = 20pF
(4pF + 36pF + 0pF) + (4pF + 36pF + 0pF) 40 + 40
80
Therefore to obtain output frequencies that are as close to this data sheets specified values as possible, in this design
example, you should specify a parallel cut crystal that is designed to work into a load of 20pF
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07068 Rev. **
05/04/2001
Page 11 of 14

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