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C9835 Schematic ( PDF Datasheet ) - Cypress Semiconductor

Teilenummer C9835
Beschreibung Low-EMI Clock Generator
Hersteller Cypress Semiconductor
Logo Cypress Semiconductor Logo 




Gesamt 18 Seiten
C9835 Datasheet, Funktion
www.DataSheet4U.com
C9835
Low-EMI Clock Generator for Intel®
Mobile 133-MHz/3 SO-DIMM Chipset Systems
Features
• Meets Intel’sMobile 133.3MHz Chipset
• Three CPU Clocks (66.6/100/133.3 MHz, 2.5V)
• Six SDRAM Clocks, 1-DCLK (100/133.3 MHz, 3.3V)
• Seven PCI Clocks (33MHz, 3.3V), one free running
• Two IOAPIC clocks, synchronous to CPU clock (33.3
MHz, 2.5V)
• One REF Clock
• Two 48-MHz fixed non-SSCG clocks (USB and DOT)
• Three 3V66 clocks (66.6 MHz, 3.3V) ICH, HUBLINK, and
AGP memory
• One selectable frequency for VCH video channel clock
(48-MHz non-SSCG, 66.6-MHz CPU-SSCG, 3.3V)
• Power management using power-down, CPU stop, and
PCI stop pins
• Three function select pins (include test-mode select)
• Cypress Spread Spectrum for best electromagnetic
interference (EMI) reduction
• SMBUS support with readback
• 56-pin SSOP and TSSOP packages
Table 1. Function Table[1]
TEST#
0
0
1
1
1
1
SEL1
X
X
0
0
1
1
SEL0
0
1
0
1
0
1
CPU(0:2)
Hi-Z
TCLK/2
66.6
100.0
133.3
133.3
SDRAM(0:5)
DCLK
Hi-Z
TCLK/2
100.0[2]
100.0[2]
133.3
100.0[2]
3V66(0:2)
Hi-Z
TCLK/3
66.6
66.6
66.6
66.6
PCIF(1:6) 48M(0:1) REF IOAPIC(0:10)
Hi-Z
TCLK/6
33.3
33.3
33.3
33.3
Hi-Z
TCLK/2
48
48
48
48
Hi-Z
TCLK
14.318
14.318
14.318
14.318
Hi-Z
TCLK/6
33.3
33.3
33.3
33.3
Note:
1. These are the frequencies that are selectable after power up using the SEL1 and SEL0 hardware pins. Other frequencies may be chosen using the devices
SMBUS interface. See the expanded frequency for a complete listing of all of the availible frequencies.
2. Will be set to 133MHz, when SMBUS Byte3, Bit 0 is set to logic 1.
Block Diagram
Pin Configuration
X IN
XO U T
TEST#
S E L 0 ,1
P C I_ S T P #
C P U _S T P #
PD#
S C LK
SDATA
36pF
36pF
IO A P IC
CPU
R in
tris ta te
s0
PD#
SDRAM
3V66
i2 c -c lk
i2 c -d a ta
PLL1
R in
48
PD#
i2 c -c lk
i2 c -d a ta
PLL2
PCI
VDD
1
VDD
1
VDDI
REF
VC H _C LK
2 IO A P IC (0 ,1 )
VDDC
3 C P U (0:2 )
VDDS
6
VDD
3
VDDP
S D R A M (0 :5 )
3 V 6 6 (0 :2 )
P C I_ F
VDDP
6 P C I(1 :6 )
VDD
2 4 8 M (0 ,1 )
VDDS
1 D C LK
REF
VDD
XIN
XOUT
VSS
VSS
3V66_0
3V66_1
3 V 66 _2(A G P )
VDD
P C I_S T P #
PCI_F
PCI1
VSS
PCI2
PCI3
VDDP
PCI4
PCI5
PCI6
VSS
AVDD
AVSS
VSS
4 8M 0(U S B )
48 M 1(D O T )
VDD
SEL0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56 VSS
55 IOAPIC0
54 IOAPIC1
53 VDDI
52 CPU0
51 VDDC
50 CPU1
49 CPU2
48 VSS
47 VSS
C
46
45
SDRAM0
SDRAM1
9 44 VDDS
8 43 SDRAM2
3
42
41
SDRAM3
VSS
5 40 SDRAM4
39 SDRAM5
38 DCLK
37 VDDS
36 VCH_CLK
35 VDD
34 CPU_STP#
33 TEST#
32 PD#
31 SCLK
30 SDATA
29 SEL1
Cypress Semiconductor Corporation 3901 North First Street San Jose CA 95134 408-943-2600
Document #: 38-07303 Rev. **
Revised April 5, 2002






C9835 Datasheet, Funktion
Clock Phase
0ns
10ns
CPU CLOCK 66MHz
CPU CLOCK 100MHz
CPU CLOCK 133MHz
DCLK/SDRAM CLOCK 100MHz
0ns
DCLK/SDRAM CLOCK 133MHz
3V66 CLOCK 66MHz 1.5ns~3.5
PCI CLOCK 33MHz
IOAPIC CLOCK 33MHz
7.5ns
C9835
20ns
30ns
40ns
2.5ns
5ns
0ns
5ns
Sync
0ns
3.75ns
0nS
3.75ns
Figure 4.
Table 4. Group Timing Relationships and Tolerances
CPU to SDRAM/DCLK
CPU to 3V66
SDRAM/DCLK to 3V66
3V66 to PCI
PCI to IOAPIC
48M (0,1)
CPU to SDRAM/DCLK
CPU to 3V66
SDRAM/DCLK to 3V66
3V66 to PCI
PCI to IOAPIC
48M (0,1)
CPU to SDRAM/DCLK
CPU to 3V66
SDRAM/DCLK to 3V66
3V66 to PCI
PCI to IOAPIC
48M (0,1)
Offset (ns)
2.5
7.5
0
1.53.5
0
Async
Offset (ns)
5
5
0
1.53.5
0
Async
Offset(ns)
0
0
0
1.53.5
0
Async
CPU = 66.6 MHz, SDRAM = 100 MHz
Tolerance (ps)
Conditions
500
500 180 degrees phase shift
500 When rising edges line up
500 3V66 leads
1000
N/A
CPU = 100 MHz, SDRAM = 100 MHz
Tolerance (ps)
Conditions
500 180 degrees phase shift
500 CPU leads
500 When rising edges line up
500 3V66 leads
1000
N/A
CPU = 133.3 MHz, SDRAM = 100 MHz
Tolerance(ps)
Conditions
500 When rising edges line up
500
500 When rising edges line up
500 3V66 leads
1000
N/A
Document #: 38-07303 Rev. **
Page 6 of 18

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C9835 pdf, datenblatt
C9835
AC Parameters
Parameter
Description
133 MHz Host
Min. Max.
100 MHz Host
Min. Max.
66 MHz Host
Min. Max.
Units
CPU
TPeriod
THIGH
TLOW
Tr / Tf
TSKEW
TCCJ
CPU(0:2) period[25,26]
CPU(0:2) high time[30]
CPU(0:2) low time[31]
CPU(0:2) rise and fall times[27]
CPU0 to any CPU Skew[26,29]
CPU(0:2) Cycle to Cycle Jitter[26,29]
7.5 8.0 10.0 10.5 15.0 15.5
1.87 3.0
5.2
1.67 2.8
5.0
0.4 1.6 0.4 1.6 0.4 1.6
150 150 150
250 250 250
ns
ns
ns
ns
ps
ps
SDRAM
TPeriod
SDRAM(0:5) 100 MHz and DCLK
period[25,26]
10.0 10.5 10.0 10.5 10.0 10.5
ns
THIGH
SDRAM(0:5) 100 MHz and DCLK high
time[30]
3.0
3.0
3.0
ns
TLOW
SDRAM(0:5) 100 MHz and DCLK low
time[31]
2.8
2.8
2.8
ns
Tr / Tf
SDRAM(0:5) 100 MHz and DCLK rise and
fall times[27]
0.4
1.6
0.4
1.6
0.4
1.6
ns
TSKEW
SDRAM(0:5) 100 MHzand DCLK
Skew[26,29]
250 250 250 ps
TCCJ
SDRAM(0:5) 100 MHz, DCLK Cycle to
Cycle Jitter[26,29]
250 250 250 ps
IOAPIC
TPeriod
THIGH
TLOW
Tr / Tf
TSKEW
TCCJ
IOAPIC(0,1) period[25,26]
IOAPIC(0,1) high time[30]
IOAPIC(0,1) low time[31]
IOAPIC(0,1) rise and fall times[27]
IOAPIC(0,1) Skew[26,29]
IOAPIC(0,1) Cycle to Cycle Jitter[26,29]
30.0 30.0 30.0
12.0 12.0 12.0
12.0 12.0 N/S 12.0
0.4 1.6 0.4 1.6 0.4 1.6
250 250 250
500 500 500
ns
ns
ns
ns
ps
ps
3V66
TPeriod
THIGH
TLOW
Tr / Tf
TSKEW
TCCJ
3V66-(0:2) period[25,26]
3V66-(0:2) high time[30]
3V66-(0:2) low time[31]
3V66-(0:2) rise and fall times[28]
(Any 3V66) to (any 3V66) Skew[26,29]
3V66-(0:2) Cycle to Cycle Jitter[26,29]
15.0 16.0 15.0 16.0 15.0 16.0
5.25 5.25 5.25
5.05 5.05 5.05
0.5 2.0 0.5 2.0 0.5 2.0
175 175 175
500 500 500
ns
ns
ns
ns
ps
ps
PCI_F
TPeriod
THIGH
PCI(_F,1:6) period[25,26]
PCI(_F, 1:6) high time[30]
30.0 30.0 30.0
12.0 12.0 12.0
ns
ns
Notes:
25. This parameter is measured as an average over 1us duration, with a crystal center frequency of 14.31818 MHz.
26. All outputs loaded per Table 6. Probes are placed on the pins and taken at 1.5V levels for 3.3V signals and at 1.25V for 2.5V signals (see Figure 8).
27. Probes are placed on the pins, and measurements are acquired between 0.4V and 2.4V for 3.3V signals and between 0.4V and 2.0V for 2.5V signals (see
Figure 8).
28. Measured from when both SEL1 and SEL0 are switched to high (enable).
29. This measurement is applicable with Spread ON or Spread OFF.
30. Probes are placed on the pins, and measurements are acquired at 2.4V for 3.3V signals and at 2.0V for 2.5V signals (see Figure 8).
31. Probes are placed on the pins, and measurements are acquired at 0.4V.
Document #: 38-07303 Rev. **
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