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AD9929 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD9929
Beschreibung CCD Signal Processor
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 30 Seiten
AD9929 Datasheet, Funktion
www.DataSheet4U.com
FEATURES
36 MSPS correlated double sampler (CDS)
12-bit 36 MHz A/D converter
On-chip vertical driver for CCD image sensor
On-chip horizontal driver for CCD image sensor
6 dB to 40 dB variable gain amplifier (VGA)
Black level clamp with variable level control
Complete on-chip timing generator
Precision Timing core with 0.58 ns resolution
2-phase H-clock modes
4-phase vertical transfer clocks
Electronic and mechanical shutter modes
On-chip sync generator with external sync option
64-lead, plastic ball, 9 × 9 grid array Pb-free package
APPLICATION
Digital still cameras
Digital video camcorders
CCD Signal Processor with
Precision Timing™ Generator
AD9929
PRODUCT DESCRIPTION
The AD9929 is a highly integrated CCD signal processor for
digital still camera and digital video camera applications. It
includes a complete analog front end with A/D conversion,
combined with a full-function, programmable timing generator.
The AD9929 also includes horizontal and vertical clock drivers,
which allow direct connection to the CCD image sensor.
The AD9929 is specified at pixel rates of up to 36 MHz. The
analog front end includes black level clamping, a CDS, a VGA,
and a 12-bit A/D converter. The timing generator provides all
the necessary CCD clocks: RG-clock, H-clocks, V-clocks, sensor
gate pulses, a substrate clock, and a substrate bias pulse. Oper-
ation is programmed using a 3-wire serial interface.
The AD9929 is packaged in a 64-lead CSPBGA. It is specified
over an operating temperature range of 25°C to +85°C.
FUNCTIONAL BLOCK DIAGRAM
REFT REFB
CCDIN
AD9929
CDS
6dB TO 40dB
VGA
VREF
ADC
12
DOUT
VSUB
RG
H1, H2
V1, V2,
V3, V4
SUBCK
HORIZONTAL
DRIVERS
2
4
VERTICAL
DRIVERS
INTERNAL CLOCKS
PRECISION
TIMING
GENERATOR
SYNC
GENERATOR
CLAMP
INTERNAL
REGISTERS
DCLK1
FD/DCLK2
MSHUT
STROBE
HD VD SYNC CLI
Figure 1.
SL SCKS DI
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.






AD9929 Datasheet, Funktion
AD9929
Parameter
V2 and V4 Outputs (See Figure 43)
Delay Times
VL to VM2
VM2 to VL
Rise Times
VL to VM2
Fall Times
VM2 to VL
Output Currents
V2 or V2 @ VL =−7.25 V
V2 or V4 @ VM2 = −0.25 V
SUBCK Output (See Figure 44)
Delay Times
VL to VH2
VH2 to VL
Rise Times
VL to VH2
Fall Times
VH2 to VL
Output Currents
SUBCK @ VL = −7.25 V
SUBCK @ VH2 = 14.75 V
Symbol
Min
tPLM2
tPML2
tR3
tF3
tPLH
tPHL
tR4
tF4
Typ
100
50
500
500
10.0
−5.0
100
50
90
90
5.4
−4.0
Max Unit
ns
ns
ns
ns
mA
mA
ns
ns
ns
ns
mA
mA
Rev. A | Page 6 of 64

6 Page









AD9929 pdf, datenblatt
AD9929
Address
0x0A
(VD
SyncReg)1
0x0B
(VD
SyncReg)1
Content
23
22
(21:16)
(15:12)
(11:10)
9
8
(7:4)
(3:2)
1
0
(23:22)
21
20
(19:17)
16
Bit
Width
1
1
6
4
2
1
1
4
2
1
1
2
1
1
3
1
Default
Value
0
0
0x00
0
0
0
0
C
3
0
0
0
1
1
0
0
0x0C
(VD
SyncReg)1
0x0D
(VD
SyncReg)1
0x0E
(VD
SyncReg)1
0x0F
0x17
0x18
0x19
0x1A
15
(14:12)
11
(10:0)
(23:21)
20
(19:18)
17
16
15
(14:12)
11
(10:0)
(23:17)
16
(15:11)
(10:0)
(23:22)
(21:20)
(19:18)
17
16
(15:10)
(9:0)
(23:8)
(7:0)
(23:13)
(12:0)
(23:13)
(12:0)
(23:13)
(12:0)
(23:13)
(12:0)
1
3
1
11
3
1
2
1
1
1
3
1
11
7
1
5
11
2
2
2
1
1
6
10
16
8
11
13
11
13
11
13
11
13
0
0
0
0x7FF
0
0
0
0
0
0
0
0
0x000
0
0x000
0
0
0
0
0
0x00
0x000
0
60
0x1FFF
0x1FFF
0x1FFF
0x1FFF
Register Name
Unused
FDPOL
XVSGMASK
SYNCCNT
SVREP_MODE
HBLKEXT
HPULSECNT
SPATLOGIC
SVOS
SPAT_EN
MODE
Unused
XSUBCK_EN
XVSG_EN
Unused
STROBE_EN
Unused
XSUBCKNUM_HP
Unused
XSUBCKNUM
Unused
MSHUTINIT
Unused
Unused
MSHUTEN
Unused
MSHUTPOS_HP
Unused
MSHUTPOS
Unused
VSUBPOL
Unused
VSUBTOG
Unused
TESTMODE1
Unused
TESTMODE2
TESTMODE3
Unused
VGAGAIN
Unused
XVSGLEN_1
Unused
XV1SPAT_TOG1
Unused
XV1SPAT_TOG2
Unused
XV2SPAT_TOG1
Unused
XV2SPAT_TOG2
Register Description
FD Polarity Control (0 = Low, 1 = High)
XVSG Masking (See Table 25)
External SYNC Setting
Super Vertical Repetition Mode
H Pulse Blanking Extend Control
H Pulse Control During Blanking
SPAT Logic Setting (See Table 27)
Second V Output Setting (10 = Ouput Repetition 1)
SPAT Control (0 = SPAT Disable, 1 = SPAT Enable)
Mode Control Bit (0 = Mode_A, 1 = Mode_B)
XSUBCK Output Enable Control (0 = Disable, 1 = Enable)
XVSG Output Enable Control (0 = Disable, 1 = Enable)
STROBE Output Control (0 = STROBE Output Held Low,
1 = STROBE Output Enabled)
High Precision Shutter XSUBCLK Pulse Position/Number
Total Number of XSUBCKs Per Field
MSHUT Initialize (1 = Forces MSHUT Low)
MSHUT Control (0 = MSHUT Held at Last State, 1 = MSHUT Output)
MSHUT Position during High Precision Operation
MSHUT Position during Normal Operation
VSUB Active Polarity (0 = Low, 1 = High)
VSUB Toggle Position. Active Starting Line in any Field.
This Register Should Always Be Set = 0.
This Register Should Always Be Set = 0.
This Register Should Always Be Set = 0.
VGA Gain
XVSGTOG_1 Pulse Width
XV1SPAT Toggle Position #1 (Mode_A Active)
XV1SPAT Toggle Position #2 (Mode_A Active)
XV2SPAT Toggle Position #1 (Mode_A Active)
XV2SPAT Toggle Position #2 (Mode_A active)
Rev. A | Page 12 of 64

12 Page





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