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PDF AD9925 Data sheet ( Hoja de datos )
| Número de pieza | AD9925 | |
| Descripción | CCD Signal Processor | |
| Fabricantes | Analog Devices | |
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CCD Signal Processor with Vertical Driver
and Precision Timing ™ Generator
AD9925
FEATURES
Integrated 10-channel V-driver
Register-compatible with the AD9991 and AD9995
3-field (6-phase) vertical clock support
2 additional vertical outputs for advanced CCDs
Complete on-chip timing generator
Precision Timing core with <600 ps resolution
Correlated double sampler (CDS)
6 dB to 42 dB 10-bit variable gain amplifier (VGA)
12-bit 36 MHz ADC
Black level clamp with variable level control
On-chip 3 V horizontal and RG drivers
2-phase and 4-phase H-clock modes
Electronic and mechanical shutter support
On-chip driver for external crystal
On-chip sync generator with external sync input
8 mm × 8 mm CSPBGA package with 0.65 mm pitch
APPLICATIONS
Digital still cameras
Digital video camcorders
CCD camera modules
GENERAL DESCRIPTION
The AD9925 is a complete 36 MHz front end solution for digi-
tal still camera and other CCD imaging applications. Based on
the AD9995 product, the AD9925 includes the analog front end
and a fully programmable timing generator (AFETG), combined
with a 10-channel vertical driver (V-driver). A Precision Timing
core allows adjustment of high speed clocks with approximately
600 ps resolution at 36 MHz operation.
The on-chip V-driver supports up to 10 channels for use with
3-field (6-phase) CCDs. Two additional vertical outputs can be
used with CCDs that contain advanced video readout modes.
Voltage levels of up to +15 V and −8 V are supported.
The analog front end includes black level clamping, CDS, VGA,
and a 12-bit ADC. The timing generator and V-driver provide
all the necessary CCD clocks: RG, H-clocks, vertical clocks,
sensor gate pulses, substrate clock, and substrate bias control.
The internal registers are programmed using a 3-wire serial
interface.
Packaged in an 8 mm × 8 mm CSPBGA, the AD9925 is speci-
fied over an operating temperature range of −25°C to +85°C.
CCDIN
RG
H1 TO H4
V1, V2
V3A, V3B
V4, V6
V5A, V5B
V7, V8
SUBCK
FUNCTIONAL BLOCK DIAGRAM
REFT REFB
0dB, –2dB, –4dB
CDS
6dB TO 42dB
VGA
VREF
12-BIT
ADC
CLAMP
INTERNAL CLOCKS
AD9925
12
DOUT
DCLK
HORIZONTAL
4 DRIVERS
XV1 TO XV8
8
10 XSG1 TO XSG6
V-DRIVER
6
VERTICAL
TIMING
CONTROL
SUBCK
PRECISION
TIMING
GENERATOR
SYNC
GENERATOR
INTERNAL
REGISTERS
MSHUT
STROBE
SL
SDI
SCK
RSTB
VSUB
HD VD SYNC CLI CLO
Figure 1.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.
1 page  
VERTICAL DRIVER SPECIFICATIONS
VDVDD = 3.3 V, VH = 15 V, VM = 0 V, VL = −7.5 V, CL shown in load model, 25°C.
Table 3.
Parameter
3-LEVEL OUTPUTS (V1, V2, V3A, V3B, V5A, V5B)
(Simplified Load Conditions, 6000 pF to Ground)
Delay Time, VL to VM and VM to VH
Delay Time, VM to VL and VH to VM
Rise Time, VL to VM and VM to VH
Fall Time, VM to VL and VH to VM
Output Currents
At −7.25 V
At −0.25 V
At +0.25 V
At +14.75 V
2-LEVEL OUTPUTS (V4, V6, V7, V8)
(Simplified Load Conditions, 6000 pF to Ground)
Delay Time, VL to VM
Delay Time, VM to VL
Rise Time, VL to VM
Fall Time, VM to VL
Output Currents
At −7.25 V
At −0.25 V
SUBCK OUTPUT
(Simplified Load Conditions, 1000 pF to Ground)
Delay Time, VL to VH
Delay Time, VH to VL
Rise Time, VL to VH
Fall Time, VH to VL
Output Currents
At −7.25 V
At +14.75 V
SERIAL VERTICAL CLOCK RESISTANCE
GND VERTICAL CLOCK RESISTANCE
Symbol
tPLM, tPMH
tPML, tPHM
tRLM, tRMH
tFML, tFHM
tPLM
tPML
tRLM
tFML
tPLH
tPHL
tRLH
tFHL
Min
Typ
10.0
−5.0
5.0
−7.2
10.0
−5.0
5.4
−4.0
30
10
V-DRIVER
INPUT
50%
50%
V-DRIVER
OUTPUT
tRLM, tRMH, tRLH
90%
tPLM, tPMH, tPLH
10%
tPML, tPHM, tPHL
90%
tFML, tFHM, tFHL
10%
Figure 2. Definition of V-Driver Timing Specifications
Max
100
200
500
500
100
200
500
500
100
200
200
200
AD9925
Unit
ns
ns
ns
ns
mA
mA
mA
mA
ns
ns
ns
ns
mA
mA
ns
ns
ns
ns
mA
mA
Ω
Ω
Rev. A | Page 5 of 96
5 Page 
TERMINOLOGY
Differential Nonlinearity (DNL)
An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. Thus, every
code must have a finite width. No missing codes guaranteed to
12-bit resolution indicates that all 4096 codes, respectively, must
be present over all operating conditions.
Peak Nonlinearity
Peak nonlinearity, a full signal chain specification, refers to the
peak deviation of the output of the AD9925 from a true straight
line. The point used as zero scale occurs 0.5 LSB before the first
code transition. Positive full scale is defined as a Level 1 and is
0.5 LSB beyond the last code transition. The deviation is meas-
ured from the middle of each particular output code to the true
straight line. The error is then expressed as a percentage of the
2 V ADC full-scale signal. The input signal is always appropri-
ately gained up to fill the ADC’s full-scale range.
AD9925
Total Output Noise
The rms output noise is measured using histogram techniques.
The standard deviation of the ADC output codes is calculated
in LSB and represents the rms noise level of the total signal
chain at the specified gain setting. The output noise can be con-
verted to an equivalent voltage, using the relationship 1 LSB =
ADC Full Scale/2n codes, where n is the bit resolution of the
ADC. For the AD9925, 1 LSB is 0.488 mV.
Power Supply Rejection (PSR)
The PSR is measured with a step change applied to the supply
pins. The PSR specification is calculated from the change in the
data outputs for a given step change in the supply voltage.
Rev. A | Page 11 of 96
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD9925.PDF ] | |
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