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AD9923A Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD9923A
Beschreibung CCD Signal Processor
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 30 Seiten
AD9923A Datasheet, Funktion
CCD Signal Processor with V-Driver and
Precision Timing Generator
AD9923A
FEATURES
Integrated 15-channel V-driver
12-bit, 36 MHz analog-to-digital converter (ADC)
Similar register map to the AD9923
5-field, 10-phase vertical clock support
Complete on-chip timing generator
Precision Timing core with <600 ps resolution
Correlated double sampler (CDS)
6 dB to 42 dB 10-bit variable gain amplifier (VGA)
Black level clamp with variable level control
On-chip 3 V horizontal and RG drivers
2-phase and 4-phase H-clock modes
Electronic and mechanical shutter support
On-chip driver for external crystal
On-chip sync generator with external sync input
8 mm × 8 mm CSP_BGA package with 0.65 mm pitch
APPLICATIONS
Digital still cameras
GENERAL DESCRIPTION
The AD9923A is a complete 36 MHz front-end solution for
digital still cameras and other CCD imaging applications.
Similar to the AD9923 product, the AD9923A includes the
analog front end (AFE), a fully programmable timing generator
(TG), and a 15-channel vertical driver (V-driver). A Precision
Timing™core allows adjustment of high speed clocks with
approximately 600 ps resolution at 36 MHz operation.
The on-chip V-driver supports up to 15 channels for use with
5-field, 10-phase CCDs.
The analog front end includes black level clamping, CDS, VGA,
and a 12-bit ADC. The timing generator and V-driver provide
all the necessary CCD clocks: RG, H-clocks, vertical clocks, sensor
gate pulses, substrate clock, and substrate bias control. The
internal registers are programmed using a 3-wire serial
interface.
Packaged in an 8 mm × 8 mm CSP_BGA, the AD9923A is
specified over an operating temperature range of −25°C to +85°C.
FUNCTIONAL BLOCK DIAGRAM
REFT REFB
–3dB, 0dB, +3dB, +6dB +6dB TO +42dB
CCDIN
CDS
VGA
VREF
AD9923A
12-BIT
ADC
12
RG
HL
H1 TO H4
V1, V2, V3,
V4, V5A, V5B,
V6, V7A, V7B,
V8, V9, V10,
V11, V12, V13
HORIZONTAL
DRIVERS
4
15 V-DRIVER
13
XV1 TO
XV13 VERTICAL
8 TIMING
CONTROL
XSG1 TO
XSG8
2
XSUBCK,
XSUBCNT
3
INTERNAL CLOCKS
CLAMP
PRECISION
TIMING
GENERATOR
SYNC
GENERATOR
INTERNAL
REGISTERS
SUBCK
VSUB, MSHUT,
STROBE
HD
VD SYNC CLI
Figure 1.
CLO
D0 TO D11
DCLK
SL
SDI
SCK
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2006–2010 Analog Devices, Inc. All rights reserved.






AD9923A Datasheet, Funktion
Parameter
VMM to VH
VH to VMM
VMM to VLL
Rise Time
VLL to VH
VLL to VMM
VMM to VH
Fall Time
VH to VLL
VH to VMM
VMM to VLL
Output Currents
at −7.25 V
at −0.25 V
at +0.25 V
at +14.75 V
RON
Conditions/Comments
AD9923A
Symbol
tPMH
tPHM
tPML
tRLH
tRLM
tRMH
tFHL
tFHM
tFML
Min Typ Max Unit
25 ns
30 ns
25 ns
40 ns
45 ns
30 ns
40 ns
90 ns
25 ns
20
12
12
20
35
mA
mA
mA
mA
Ω
V-DRIVER
INPUT
50%
50%
V-DRIVER
OUTPUT
tRLM, tRMH, tRLH
90%
tPLM, tPMH, tPLH
10%
tPML, tPHM, tPHL
90%
tFML, tFHM, tFHL
10%
Figure 2. Definition of V-Driver Timing Specifications
ANALOG SPECIFICATIONS
AVDD = 3.0 V, fCLI = 36 MHz, typical timing specifications, TMIN to TMAX, unless otherwise noted.
Table 5.
Parameter
CDS
Allowable CCD Reset Transient
CDS Gain Accuracy
−3 dB CDS Gain
0 dB CDS Gain
+3 dB CDS Gain
+6 dB CDS Gain
Maximum Input Range Before Saturation
0 dB CDS Gain
−3 dB CDS Gain
+6 dB CDS Gain
Maximum CCD Black Pixel Amplitude
0 dB CDS Gain (Default)
+6 dB CDS Gain
VARIABLE GAIN AMPLIFIER (VGA)
Gain Control Resolution
Gain Monotonicity
Gain Range
Minimum Gain (VGA Code 15)
Maximum Gain (VGA Code 1023)
Conditions/Comments
Input characteristics definition1
VGA gain = 6 dB (Code 15, default value)
Default
Default setting
Positive offset definition1
Min Typ
0.5
−3 −2.5
0 +0.5
+3 +3.5
+5.5 +6
1.0
1.4
0.5
−100
−50
1024
Guaranteed
6
42
Max Unit
1.2 V
−2 dB
+1 dB
+4 dB
+6.5 dB
V p-p
V p-p
V p-p
+200 mV
+100 mV
Steps
dB
dB
Rev. A | Page 5 of 84

6 Page









AD9923A pdf, datenblatt
TYPICAL PERFORMANCE CHARACTERISTICS
450
400
3.3V
350
3.0V
300
250
2.7V
200
150
100
50
0
18 27
FREQUENCY (MHz)
Figure 5. Power vs. Sample Rate
36
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
0
500 1000 1500 2000 2500 3000 3500 4000
CODE
Figure 6. Typical DNL Performance
AD9923A
5
4
3
2
1
0
–1
–2
–3
0 500 1000 1500 2000 2500 3000 3500 4000
CODE
Figure 7. Typical INL Performance
55
50
+6dB
45
40
35
+3dB
30
–3dB
25
20
15
0dB
10
5
0
0 100 200 300 400 500 600 700 800 900 1000
GAIN CODE
Figure 8. Output Noise vs. VGA Gain
Rev. A | Page 11 of 84

12 Page





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