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AD9707 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD9707
Beschreibung (AD9704 - AD9707) TxDAC D/A Converters
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 30 Seiten
AD9707 Datasheet, Funktion
Data Sheet
8-/10-/12-/14-Bit, 175 MSPS TxDAC
Digital-to-Analog Converters
AD9704/AD9705/AD9706/AD9707
FEATURES
175 MSPS update rate
Low power member of pin-compatible
TxDAC product family
Low power dissipation
12 mW at 80 MSPS, 1.8 V
50 mW at 175 MSPS, 3.3 V
Wide supply voltage: 1.7 V to 3.6 V
SFDR to Nyquist
AD9707: 84 dBc at 5 MHz output
AD9707: 83 dBc at 10 MHz output
AD9707: 75 dBc at 20 MHz output
Adjustable full-scale current outputs: 1 mA to 5 mA
On-chip 1.0 V reference
CMOS-compatible digital interface
Common-mode output: adjustable 0 V to 1.2 V
Power-down mode <2 mW at 3.3 V (SPI controllable)
Self-calibration
Compact 32-lead LFCSP_VQ, RoHS compliant package
GENERAL DESCRIPTION
The AD9704/AD9705/AD9706/AD9707 are the fourth-generation
family in the TxDAC series of high performance, CMOS digital-to-
analog converters (DACs). This pin-compatible, 8-/10-/12-/14-bit
resolution family is optimized for low power operation, while
maintaining excellent dynamic performance. The AD9704/
AD9705/AD9706/AD9707 family is pin-compatible with the
AD9748/AD9740/AD9742/AD9744 family of TxDAC converters
and is specifically optimized for the transmit signal path of
communication systems. All of the devices share the same
interface, LFCSP_VQ package, and pinout, providing an upward or
downward component selection path based on performance,
resolution, and cost. The AD9704/AD9705/AD9706/AD9707
offers exceptional ac and dc performance, while supporting
update rates up to 175 MSPS.
The flexible power supply operating range of 1.7 V to 3.6 V and low
power dissipation of the AD9704/AD9705/AD9706/AD9707 parts
make them well-suited for portable and low power applications.
Power dissipation of the AD9704/AD9705/AD9706/AD9707 can
be reduced to 15 mW, with a small trade-off in performance, by
lowering the full-scale current output. In addition, a power-down
mode reduces the standby power dissipation to approximately
2.2 mW.
The AD9704/AD9705/AD9706/AD9707 has an optional serial
peripheral interface (SPI®) that provides a higher level of program-
mability to enhance performance of the DAC. An adjustable
output, common-mode feature allows for easy interfacing to
other components that require common modes from 0 V to 1.2 V.
Edge-triggered input latches and a 1.0 V temperature-compensated
band gap reference have been integrated to provide a complete,
monolithic DAC solution. The digital inputs support 1.8 V and
3.3 V CMOS logic families.
PRODUCT HIGHLIGHTS
1. Pin Compatible. The AD9704/AD9705/AD9706/AD9707
line of TxDAC® converters is pin-compatible with the
AD9748/AD9740/AD9742/AD9744 TxDAC line
(LFCSP_VQ package).
2. Low Power. Complete CMOS DAC operates on a single
supply of 3.6 V down to 1.7 V, consuming 50 mW (3.3 V)
and 12 mW (1.8 V). The DAC full-scale current can be
reduced for lower power operation. Sleep and power-down
modes are provided for low power idle periods.
3. Self-Calibration. Self-calibration enables true 14-bit INL
and DNL performance in the AD9707.
4. Twos Complement/Binary Data Coding Support. Data
input supports twos complement or straight binary data
coding.
5. Flexible Clock Input. A selectable high speed, single-ended,
and differential CMOS clock input supports 175 MSPS
conversion rate.
6. Device Configuration. Device can be configured through
pin strapping, and SPI control offers a higher level of
programmability.
7. Easy Interfacing to Other Components. Adjustable
common-mode output allows for easy interfacing to other
signal chain components that accept common-mode levels
from 0 V to 1.2 V.
8. On-Chip Voltage Reference. The AD9704/AD9705/AD9706/
AD9707 include a 1.0 V temperature-compensated band
gap voltage reference.
9. Industry-Standard 32-Lead LFCSP_VQ Package.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2006–2011 Analog Devices, Inc. All rights reserved.






AD9707 Datasheet, Funktion
AD9704/AD9705/AD9706/AD9707
Data Sheet
AD9707
Parameter
Min Typ Max
Supply Current Power-Down
Mode (IAVDD)
0.7 7.5
Supply Current Clock Power-
Down Mode (IDVDD)5
0.6 1
Supply Current Clock Power-
Down Mode (ICLKVDD)5
42.5 64
Power Supply Rejection Ratio −0.2 +0.03 +0.2
(AVDD)6
OPERATING RANGE
−40 +85
AD9706
Min Typ Max
0.7 7.5
0.6 1
42.5 64
−0.2 +0.03 +0.2
−40 +85
AD9705
Min Typ Max
0.7 7.5
0.6 1
42.5 64
−0.2 +0.03 +0.2
−40 +85
AD9704
Min Typ Max
0.7 7.5
0.6 1
42.5 64
−0.2 +0.03 +0.2
−40 +85
Unit
μA
mA
μA
% of
FSR/V
°C
1 Measured at IOUTA, driving a virtual ground.
2 Normal full scale current, IOUTFS is 32 × the IREF current.
3 Use an external buffer amplifier with an input bias current <100 nA to drive any external load.
4 Measured at fCLOCK = 175 MSPS and fOUT = 1.0 MHz, using a differential clock.
5 Measured at fCLOCK = 100 MSPS and fOUT = 1.0 MHz, using a differential clock.
6 ± 5% power supply variation.
DYNAMIC SPECIFICATIONS (3.3 V)
TMIN to TMAX, AVDD = 3.3 V, DVDD = 3.3 V, CLKVDD = 3.3 V, IOUTFS = 2 mA, differential transformer coupled output, 453 Ω
differentially terminated unless otherwise noted.
Table 2.
Parameter
DYNAMIC PERFORMANCE
Maximum Output Update Rate, fCLOCK
Output Settling Time, tST (to 0.1%)1
Output Propagation Delay, tPD
Glitch Impulse
Output Rise Time (10% to 90%)1
Output Fall Time (10% to 90%)1
AC LINEARITY
Spurious-Free Dynamic Range to
Nyquist
fCLOCK = 10 MSPS, fOUT = 2.1 MHz
fCLOCK = 25 MSPS, fOUT = 2.1 MHz
fCLOCK = 65 MSPS, fOUT = 5.1 MHz
fCLOCK = 65 MSPS, fOUT = 10.1 MHz
fCLOCK = 80 MSPS, fOUT = 1.0 MHz
fCLOCK = 125 MSPS, fOUT = 15.1 MHz
fCLOCK = 125 MSPS, fOUT = 25.1 MHz
fCLOCK = 175 MSPS, fOUT = 20.1 MHz
fCLOCK = 175 MSPS, fOUT = 40.1 MHz
Noise Spectral Density
fCLOCK = 175 MSPS, fOUT = 6.0 MHz,
IOUTFS = 2 mA
fCLOCK = 175 MSPS, fOUT = 6.0 MHz,
IOUTFS = 5 mA
fCLOCK = 175 MSPS, fOUT = 6.0 MHz,
IOUTFS = 1 mA
AD9707
AD9706
AD9705
AD9704
Min Typ Max Min Typ Max Min Typ Max Min Typ Max Unit
175
11
4
5
2.5
2.5
175
11
4
5
2.5
2.5
175
11
4
5
2.5
2.5
175
11
4
5
2.5
2.5
MSPS
ns
ns
pV-s
ns
ns
84
84
84
83
74 83
78
77
75
72
−152
−161
−146
84
83
84
83
72 82
78
77
75
71
−152
84
84
84
83
72 82
78
76
75
71
−144
70
68
70
71
66 70
68
69
69
67
−136
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc/Hz
dBc/Hz
dBc/Hz
1 Measured single-ended into 500 Ω load.
Rev. B | Page 6 of 44

6 Page









AD9707 pdf, datenblatt
AD9704/AD9705/AD9706/AD9707
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
AD9707
Data Sheet
DB7 1
DB6 2
DVDD 3
DB5 4
DB4 5
DB3 6
DB2 7
DB1 8
PIN 1
INDICATOR
AD9707
TOP VIEW
(Not to Scale)
24 FS ADJ
23 REFIO
22 ACOM
21 IOUTA
20 IOUTB
19 OTCM
18 AVDD
17 PIN/SPI/RESET
NOTES
1. IT IS RECOMMENDED THAT THE EXPOSED PAD BE
THERMALLY CONNECTED TO A COPPER GROUND
PLANE FOR ENHANCED ELECTRICAL AND THERMAL
PERFORMANCE.
Figure 3. AD9707 Pin Configuration
Table 9. AD9707 Pin Function Descriptions
Pin No.
Mnemonic Description
28 to 32, 1, DB12 to DB1 Data Bit 12 to Data Bit 1.
2, 4 to 8
3
DVDD
Digital Supply Voltage (1.7 V to 3.6 V).
9
DB0 (LSB)
Least Significant Data Bit (LSB).
10, 26
DCOM
Digital Common.
11
CLKVDD
Clock Supply Voltage (1.7 V to 3.6 V).
12
CLK+
Positive Differential Clock Input.
13
CLK−
Negative Differential Clock Input.
14
CLKCOM
Clock Common.
15 CMODE/SCLK In pin mode, this pin selects the clock input type. Connect to CLKCOM for single-ended clock receiver
(drive CLK+ and float CLK–). Connect to CLKVDD for differential receiver. In SPI mode, this pin is the serial
data clock input.
16 MODE/SDIO In pin mode, this pin selects the input data format. Connect to DCOM for straight binary, and DVDD for twos
complement. In SPI mode, this pin acts as SPI data input/output.
17 PIN/SPI/RESET Selects SPI Mode or Pin Mode Operation. Active high for pin mode operation and active low for SPI mode
operation. Pulse high to reset SPI registers to default values.
18
AVDD
Analog Supply Voltage (1.7 V to 3.6 V).
19
OTCM
Adjustable Output Common Mode. Refer to the Theory of Operation section for details.
20
IOUTB
Complementary DAC Current Output. Full-scale current is sourced when all data bits are 0s.
21
IOUTA
DAC Current Output. Full-scale current is sourced when all data bits are 1s.
22
ACOM
Analog Common.
23
REFIO
Reference Input/Output. Serves as reference input when internal reference disabled. Serves as 1.0 V
reference output when internal reference is activated. Requires a 0.1 μF capacitor to ACOM when internal
reference is activated.
24
FS ADJ
Full-Scale Current Output Adjust.
25
SLEEP/CSB
In pin mode, active high powers down chip. In SPI mode, this pin is the serial port chip select (active low).
27 DB13 (MSB) Most Significant Data Bit (MSB).
EPAD
It is recommended that the exposed pad be thermally connected to a copper ground plane for enhanced
electrical and thermal performance.
Rev. B | Page 12 of 44

12 Page





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