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PDF AD9481 Data sheet ( Hoja de datos )
| Número de pieza | AD9481 | |
| Descripción | A/D Converter | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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FEATURES
DNL = ±0.35 LSB
INL = ±0.26 LSB
Single 3.3 V supply operation (3.0 V to 3.6 V)
Power dissipation of 439 mW at 250 MSPS
1 V p-p analog input range
Internal 1.0 V reference
Single-ended or differential analog inputs
De-multiplexed CMOS outputs
Power-down mode
Clock duty cycle stabilizer
APPLICATIONS
Digital oscilloscopes
Instrumentation and measurement
Communications
Point-to-point radios
Digital predistortion loops
GENERAL DESCRIPTION
The AD9481 is an 8-bit, monolithic analog-to-digital converter
(ADC) optimized for high speed and low power consumption.
Small in size and easy to use, the product operates at a
250 MSPS conversion rate, with excellent linearity and dynamic
performance over its full operating range.
To minimize system cost and power dissipation, the AD9481
includes an internal reference and track-and-hold circuit. The
user only provides a 3.3 V power supply and a differential
encode clock. No external reference or driver components are
required for many applications.
The digital outputs are TTL/CMOS-compatible with an option
of twos complement or binary output format. The output data
bits are provided in an interleaved fashion along with output
clocks that simplifies data capture.
8-Bit, 250 MSPS
3.3 V A/D Converter
AD9481
FUNCTIONAL BLOCK DIAGRAM
VREF SENSE AGND DRGND DRVDD AVDD
VIN+
VIN–
DS+
DS–
CLK+
CLK–
REFERENCE
AD9481
T AND H
8-BIT
ADC
PIPELINE
CORE
8
CLOCK
MGMT
LOGIC
PORT 8
A
D7A TO D0A
PORT 8
B
D7B TO D0B
DCO+
DCO–
PDWN
S1
Figure 1.
The AD9481 is available in a Pb-free, 44-lead, surface-mount
package (TQFP-44) specified over the industrial temperature
range (−40°C to +85°C).
PRODUCT HIGHLIGHTS
1. Superior linearity. A DNL of ±0.35 makes the AD9481
suitable for many instrumentation and measurement
applications
2. Power-down mode. A power-down function may be exercised
to bring total consumption down to 15 mW.
3. De-multiplexed CMOS outputs allow for easy interfacing
with low cost FPGAs and standard logic.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.
1 page  
AD9481
AC SPECIFICATIONS
AVDD = 3.3 V, DRVDD = 3.3 V; TMIN = −40°C, TMAX = +85°C, AIN = −1 dBFS, full scale = 1.0 V, internal reference, differential analog and
clock inputs, unless otherwise noted.
Table 3.
Parameter
SIGNAL-TO-NOISE RATIO (SNR)
fIN = 19.7 MHz
fIN = 70.1 MHz
SIGNAL-TO-NOISE AND DISTORTION (SINAD)
fIN = 19.7 MHz
fIN = 70.1 MHz
EFFECTIVE NUMBER OF BITS (ENOB)
fIN = 19.7 MHz
fIN = 70.1 MHz
WORST SECOND OR THIRD HARMONIC DISTORTION
fIN = 19.7 MHz
fIN = 70.1 MHz
WORST OTHER
fIN = 19.7 MHz
fIN = 70.1 MHz
SPURIOUS-FREE DYNAMIC RANGE (SFDR)1
fIN = 19.7 MHz
fIN = 70.1 MHz
TWO-TONE INTERMODULATION DISTORTION (IMD)
fIN1 = 69.3 MHz, fIN2 = 70.3 MHz
Temp
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
Test Level
V
I
V
I
V
I
V
I
V
I
V
I
V
AD9481-250
Min Typ
Max
Unit
46
44.5 45.7
dB
dB
45.9
44.4 45.7
dB
dB
7.5
7.2 7.5
Bits
Bits
−64.8
dBc
−64.8 −54 dBc
−68 dBc
−65.8 −56 dBc
−64.8
dBc
−64.8 −54 dBc
−64.9
dBc
1 DC and Nyquist bin energy ignored.
Rev. 0 | Page 5 of 28
5 Page 
Power Supply Rejection Ratio
The ratio of a change in input offset voltage to a change in
power supply voltage.
Signal-to-Noise and Distortion (SINAD)
The ratio of the rms signal amplitude (set 1 dB below full scale)
to the rms value of the sum of all other spectral components,
including harmonics, but excluding dc.
Signal-to-Noise Ratio (without Harmonics)
The ratio of the rms signal amplitude (set at 1 dB below full
scale) to the rms value of the sum of all other spectral
components, excluding the first five harmonics and dc.
Spurious-Free Dynamic Range (SFDR)
The ratio of the rms signal amplitude to the rms value of the
peak spurious spectral component. The peak spurious
component may or may not be a harmonic. It also may be
reported in dBc (degrades as signal level is lowered) or dBFS
(always related back to converter full scale).
Two-Tone Intermodulation Distortion Rejection
The ratio of the rms value of either input tone to the rms value
of the worst third-order intermodulation product, in dBc.
AD9481
Two-Tone SFDR
The ratio of the rms value of either input tone to the rms value
of the peak spurious component. The peak spurious component
may or may not be an IMD product. It also may be reported in
dBc (degrades as signal level is lowered) or in dBFS (always
relates back to converter full scale).
Worst Other Spur
The ratio of the rms signal amplitude to the rms value of the
worst spurious component (excluding the second and third
harmonic), reported in dBc.
Transient Response Time
The time it takes for the ADC to reacquire the analog input
after a transient from 10% above negative full scale to 10%
below positive full scale.
Out-of-Range Recovery Time
This is the time it takes for the ADC to reacquire the analog
input after a transient from 10% above positive full scale to 10%
above negative full scale, or from 10% below negative full scale
to 10% below positive full scale.
Rev. 0 | Page 11 of 28
11 Page | ||
| Páginas | Total 28 Páginas | |
| PDF Descargar | [ Datasheet AD9481.PDF ] | |
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