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AD9398 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD9398
Beschreibung Display Interface
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 30 Seiten
AD9398 Datasheet, Funktion
www.DataSheet4U.com
FEATURES
HDMI interface
Supports high bandwidth digital content protection
RGB to YCbCr 2-way color conversion
1.8 V/3.3 V power supply
100-lead, Pb-free LQFP
RGB and YCbCr output formats
Digital video interface
HDMI 1.1, DVI 1.0
150 MHz HDMI receiver
Supports high bandwidth digital content protection
(HDCP 1.1)
Digital audio interface
HDMI 1.1-compatible audio interface
SPDIF (IEC90658-compatible) digital audio output
Multichannel I2S audio output (up to 8 channels)
APPLICATIONS
Advanced TVs
HDTVs
Projectors
LCD monitors
GENERAL DESCRIPTION
The AD9398 offers a high definition multimedia interface
(HDMI) receiver integrated on a single chip. Also included is
support for high bandwidth digital content protection (HDCP).
The AD9398 contains a HDMI 1.0-compatible receiver and
supports all HDTV formats (up to 1080p) and display resolu-
tions up to SXGA (1280 × 1024 @ 75 Hz). The receiver features
an intrapair skew tolerance of up to one full clock cycle. With
the inclusion of HDCP, displays can now receive encrypted
video content. The AD9398 allows for authentication of a video
receiver, decryption of encoded data at the receiver, and
renewability of that authentication during transmission as
specified by the HDCP 1.1 protocol.
Fabricated in an advanced CMOS process, the AD9398 is
provided in a space-saving 100-lead, surface-mount, Pb-free,
plastic LQFP and is specified over the 0°C to 70°C temperature
range.
HDMI™ Display Interface
AD9398
FUNCTIONAL BLOCK DIAGRAM
SCL
SDA
Rx0+
Rx0–
Rx1+
Rx1–
Rx2+
Rx2–
RxC+
RxC–
RTERM
MCL
MDA
DDCSCL
DDCSDA
SERIAL REGISTER
AND
POWER MANAGEMENT
HDMI
RECEIVER
R/G/B 8 × 3
OR YCbCr
2 DATACK
HSYNC
VSYNC
DE
R/G/B 8 × 3
YCbCr (4:2:2
OR 4:4:4)
2
DATACK
HSOUT
VSOUT
DE
S/PDIF OUT
8-CHANNEL
I2S
MCLK
LRCLK
HDCP
Figure 1.
AD9398
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
© 2005 Analog Devices, Inc. All rights reserved.






AD9398 Datasheet, Funktion
AD9398
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
GND
GREEN 7
GREEN 6
GREEN 5
GREEN 4
GREEN 3
GREEN 2
GREEN 1
GREEN 0
VDD
GND
BLUE 7
BLUE 6
BLUE 5
BLUE 4
BLUE 3
BLUE 2
BLUE 1
BLUE 0
MCLKIN
MCLKOUT
SCLK
LRCLK
I2S3
I2S2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
PIN 1
NC = NO CONNECT
Table 5. Complete Pinout List
Pin Type
Pin No.
INPUTS
81
DIGITAL VIDEO DATA INPUTS 35
34
38
37
41
40
DIGITAL VIDEO CLOCK INPUTS 43
44
OUTPUTS
92 to 99
2 to 9
12 to 19
89
87
85
84
REFERENCES
57
AD9398
TOP VIEW
(Not to Scale)
75 GND
74 NC
73 NC
72 VD
71 NC
70 NC
69 GND
68 NC
67 VD
66 NC
65 GND
64 GND
63 GND
62 GND
61 GND
60 GND
59 PVDD
58 GND
57 FILT
56 PVDD
55 GND
54 PVDD
53 GND
52 MDA
51 MCL
Figure 2. Pin Configuration
Mnemonic
PWRDN
Rx0+
Rx0−
Rx1+
Rx1−
Rx2+
Rx2−
RxC+
RxC−
RED [7:0]
GREEN [7:0]
BLUE [7:0]
DATACK
HSOUT
VSOUT
FIELD
FILT
Function
Power-Down Control
Digital Input Channel 0 True
Digital Input Channel 0 Complement
Digital Input Channel 1 True
Digital Input Channel 1 Complement
Digital Input Channel 2 True
Digital Input Channel 2 Complement
Digital Data Clock True
Digital Data Clock Complement
Outputs of Red Converter, Bit 7 is MSB
Outputs of Green Converter, Bit 7 is MSB
Outputs of Blue Converter, Bit 7 is MSB
Data Output Clock
HSYNC Output Clock (Phase-Aligned with DATACK)
VSYNC Output Clock (Phase-Aligned with DATACK)
Odd/Even Field Output
Connection for External Filter Components For audio
PLL
Value
3.3 V CMOS
TMDS
TMDS
TMDS
TMDS
TMDS
TMDS
TMDS
TMDS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
PVDD
Rev. 0 | Page 6 of 44

6 Page









AD9398 pdf, datenblatt
AD9398
AUDIO PLL SETUP
Data contained in the audio infoframes, among other registers,
define for the AD9398 HDMI receiver not only the type of
audio, but the sampling frequency (fS). The audio infoframe also
contains information about the N and CTS values used to
recreate the clock. With this information, it is possible to
regenerate the audio sampling frequency. The audio clock is
regenerated by dividing the 20-bit CTS value into the TMDS
clock, then multiplying by the 20-bit N value. This yields a
multiple of the sampling frequency of either 128 × fS or 256 × fS.
It is possible for this to be specified up to 1024 × fS.
SOURCE DEVICE
SINK DEVICE
128 × fS
DIVIDE
BY
N
CYCLE
TIME
COUNTER
CTS1
VIDEO
CLOCK
N
REGISTER
N
TMDS
CLOCK
N1
DIVIDE
BY
CTS
MULTIPLY 128 × fS
BY
N
1N AND CTS VALUES ARE TRANSMITTED USING THE
AUDIO CLOCK REGENERATION PACKET. VIDEO
CLOCK IS TRANSMITTED ON TMDS CLOCK CHANNEL.
Figure 7. N and CTS for Audio Clock
In order to provide the most flexibility in configuring the audio
sampling clock, an additional PLL is employed. The PLL
characteristics are determined by the loop filter design, the PLL
charge pump current, and the VCO range setting. The loop
filter design is shown in Figure 8.
CP CZ PVD
8nF 80nF
RZ
1.5kΩ
FILT
Figure 8. PLL Loop Filter Detail
To fully support all audio modes for all video resolutions up
to 1080p, it is necessary to adjust certain audio-related
registers from their power-on default values. Table 9
describes these registers and gives the recommended
settings.
Table 9. AD9398 Audio Register Settings
Recommended
Register Bits Setting
Function
0x01
7:0 0x00
PLL Divisor (MSBs)
0x02
7:4 0x40
PLL Divisor (LSBs)
0x03
7:6 01
VCO Range
5:3 010
Charge Pump Current
21
PLL Enable
0x34
0x58
40
71
6:4 011
Audio Frequency Mode
Override
PLL Enable
MCLK PLL Divisor
30
2:0 0**
N/CTS Disable
MCLK Sampling Frequency
Comments
The analog video PLL is also used for the audio clock circuit when in
HDMI mode. This is done automatically.
In HDMI mode, this bit enables a lower frequency to be used for
audio MCLK generation.
Allows the chip to determine the low frequency mode of the audio
PLL.
This enables the analog PLL to be used for audio MCLK generation.
When the analog PLL is enabled for MCLK generation, another
frequency divider is provided. These bits set the divisor to 4.
The N and CTS values should always be enabled.
000 = 128 × fS
001 = 256 × fS
010 = 384 × fS
011 = 512 × fS
Rev. 0 | Page 12 of 44

12 Page





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