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AD71028 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD71028
Beschreibung Dual Digital BTSC Encoder
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 20 Seiten
AD71028 Datasheet, Funktion
www.DataSheet4U.com
FEATURES
2 complete independent BTSC encoders
Pilot tone generator
Includes subcarrier modulation
Typical 23 dB to 27 dB separation, 16 dB minimum
Signal bandwidth of 14 kHz
Phat-StereoTM algorithm for stereo image enhancement
Dialog enhancement function for playing wide dynamic
range video sources over built-in TV speakers
Includes L-R dual-band compressor
SPI® port for control of modes and effects
Differential output for optimum performance
DAC performance: 92 dB dynamic range, –92 dB THD+N
Output level control for setting aural carrier deviation
Flexible serial data port with right-justified, left-justified,
I2S compatible, and DSP serial port modes
48-lead LQFP plastic package
APPLICATIONS
Digital set-top box BTSC encoder
Dual Digital BTSC Encoder
with Integrated DAC
AD71028
PRODUCT OVERVIEW
The AD71028 dual digital BTSC encoder provides two complete
digital BTSC encoder channels, including the pilot-tone
generation and subcarrier mixing functions. Two built-in high
performance DACs are provided to output the BTSC baseband
composite signal. The output of the AD71028 can be connected
with minimal external circuitry to the input of a 4.5 MHz aural
FM modulator.
In addition to the BTSC encoders, the AD71028 also includes a
stereo image enhancement function, Phat Stereo, to increase the
sense of spaciousness available from closely spaced TV
loudspeakers. A dialog enhancement algorithm is also included
to solve the problem of playing wide dynamic range sources
over limited-performance TV speakers and amplifiers. An
extensive SPI port allows click-free parameter updates.
The AD71028 also includes ADI’s patented multibit Σ-∆ DAC
architecture. This architecture provides 92 dB SNR and THD+N
of –92 dB.
SERIAL 3
INPUT A
CLOCK
SIGNAL
GROUP
SERIAL 3
INPUT B
SPI I/O
GROUP
4
FUNCTIONAL BLOCK DIAGRAM
PLL DIVIDERS
SERIAL
INPUT
CLOCK
DOUBLER
BTSC
ENCODER
CORE A
PLL DIVIDERS
CLOCK
DOUBLER
SERIAL
INPUT
BTSC
ENCODER
CORE B
SPI PORT
CONTROL REGISTERS
PARAMETER RAM
Figure 1. Functional Block Diagram
DAC
BIAS
DAC
AD71028
BTSC
ENCODED
OUTPUT A
ANALOG
BIAS
BTSC
ENCODED
OUTPUT B
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.






AD71028 Datasheet, Funktion
AD71028
PIN CONFIGURATION AND FUNCTIONAL DESCRIPTIONS
48 47 46 45 44 43 42 41 40 39 38 37
DIV2_PA 1
DIV1_PB 2
DIV2_PB 3
NC 4
NC 5
DGND 6
DVDD 7
ODVDD 8
NC 9
NC 10
COUT 11
CDATA 12
AD71028
TOP VIEW
(Not to Scale)
36 AGND
35 OUTB–
34 OUTB+
33 AVDD
32 AGND
31 AVDD
30 OUTA+
29 OUTA–
28 AGND
27 NC
26 NC
25 DOUBLE
13 14 15 16 17 18 19 20 21 22 23 24
NC = NO CONNECT
Figure 2. 48-Lead Low Profile Quad Flat Pack (LQFP)
Table 9. Pin Function Descriptions
Pin No.
Mnemonic
1 DIV2_PA
2 DIV1_PB
3 DIV2_PB
4, 5, 9, 10, 26, 27, 39 NC
6, 16, 44
DGND
7, 13, 17, 45
DVDD
8 ODVDD
11 COUT
12 CDATA
14 CCLK
15 CLATCH
18 RESETB
19 SDATA_PA
20 BCLK_PA
21 LRCLK_PA
22 SDATA_PB
23 BCLK_PB
24 LRCLK_PB
25 DOUBLE
28, 32, 36
AGND
29 OUTA–
30 OUTA+
31, 33
AVDD
34 OUTB+
35 OUTB–
37 REFCAP
38 FILTCAP
Input/Output
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
IN
IN
Description
CLK27_PA clock (Pin 40) Divided by 1125
PLL_PB Clock (Pin 46) Divided by 512 (DOUBLE = 1) or 1024 (DOUBLE = 0)
CLK27_PB Clock (Pin 41) Divided by 1125
No Connection
Digital Ground
Digital Supply for DSP Core
Digital Supply for Output Buffers
SPI Readback
SPI Control Data Input
SPI Serial Bit Clock
SPI Control Latch Signal
Reset Signal for Both Processors, Active Low
Data Input to Processor A
Bit Clock Signal for Serial Data Input to Processor A
Left/Right Framing Signal for Data Input to Processor A
Data Input to Processor B
Bit Clock Signal for Serial Data Input to Processor B
Left/Right Framing Signal for Data Input to Processor B
Enables Internal Clock Doubler for 12.288 MHz Input (Both Processors)
Analog Ground
Negative Analog Output, Processor A
Positive Analog Output, Processor A
Analog Supply
Positive Analog Output, Processor B
Negative Analog Output, Processor B
Connection Point for 10 µF VREF Filter Capacitor
Connection for Noise Reduction Capacitor
Rev. 0 | Page 6 of 20

6 Page









AD71028 pdf, datenblatt
AD71028
SPI PORT
CLATCH
CCLK
CDATA
CLATCH
BYTE 0
BYTE 1
Figure 5. Sample of SPI Write Format (Single-Write Mode)
BYTE 4
CCLK
CDATA
COUT
BYTE 0
BYTE 1
XXX
HI-Z
DATA
DATA
Figure 6. Sample of SPI Read Format (Single-Read Mode)
DATA
HI-Z
OVERVIEW
The AD71028 can be controlled using the SPI port. In general,
there are three parameters per processor that can be controlled:
the encoder output level, the Phat Stereo image enhancement
algorithm, and the dialog enhancement algorithm. It is also
possible to write new data into the parameter RAM to alter the
filter coefficients used in the BTSC encoding process. This is a
fairly complex topic unnecessary for normal operation of the
chip, and the details are not included in this data sheet. Please
contact ADI if modifications to the BTSC filters are required.
The SPI port uses a 4-wire interface consisting of CLATCH,
CCLK, CDATA, and COUT signals. The CLATCH signal goes
low at the beginning of a transaction and high at the end of a
transaction. The CCLK signal latches the serial input data on a
low-to-high transition. The CDATA signal carries the serial
input data, and the COUT signal is the serial output data. The
COUT signal remains three-stated until a READ operation is
requested. This allows other SPI compatible peripherals to share
the same readback line. All SPI transactions follow the same
basic format, shown in Figure 5. Figure 6 shows the read format.
The Wb/R bit is low for a write and high for a read operation.
The 10-bit address word is decoded into either a location in the
parameter RAM or one of the SPI registers. The number of data
bytes varies according to the register or memory being accessed.
The detailed data format diagram for continuous-mode
operation is given in the SPI Read/Write Data Formats section.
SPI ADDRESS DECODING
Table 11 shows the address decoding used in the SPI port. The
SPI address space encompasses a set of registers and the param-
eter RAM. The parameter RAM is loaded on power-up from an
on-board boot ROM.
Table 11. SPI Port Address Decoding
SPI Address
Register Name
0–255
Parameter RAM Processor A
256 SPI Control Register Processor A
257 Reserved
258 Output Level Processor A
259 Stereo Spreading Control Processor A
260 Dialog Enhancement Control Processor A
512–767
Parameter RAM Processor B
768 SPI Control Register Processor B
769 Reserved
770 Output Level Processor B
771 Stereo Spreading Control Processor B
772 Dialog Enhancement Control Processor B
Read/Write Word Length
Write: 22 Bits, Read: 22 Bits
Write: 11 Bits, Read: N/A
Write: 22 Bits, Read: N/A
Write: 22 Bits, Read: N/A
Write: 22 Bits, Read: N/A
Write: 22 Bits, Read: 22 Bits
Write: 22 Bits, Read: N/A
Write: 22 Bits, Read: N/A
Write: 22 Bits, Read: N/A
Write: 22 Bits, Read: N/A
Rev. 0 | Page 12 of 20

12 Page





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