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PCA9698 Schematic ( PDF Datasheet ) - NXP Semiconductors

Teilenummer PCA9698
Beschreibung 40-bit Fm+ I2C-bus advanced I/O port
Hersteller NXP Semiconductors
Logo NXP Semiconductors Logo 




Gesamt 30 Seiten
PCA9698 Datasheet, Funktion
www.DataSheet4U.com
PCA9698
40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT
Rev. 02 — 19 July 2006
Product data sheet
1. General description
The PCA9698 provides 40-bit parallel input/output (I/O) port expansion for I2C-bus
applications organized in 5 banks of 8 I/Os. At 5 V supply voltage, the outputs are capable
of sourcing 10 mA and sinking 25 mA with a total package load of 1 A to allow direct
driving of 40 LEDs. Any of the 40 I/O ports can be configured as an input or output.
The PCA9698 is the first GPIO device in a new Fast-mode Plus (Fm+) family. Fm+
devices offer higher frequency (up to 1 MHz) and longer, more densely populated bus
operation (up to 4000 pF).
The device is fully configurable: output ports can be programmed to be totem-pole or
open-drain and logic states can change at either the Acknowledge (bank change) or the
Stop Command (global change), each input port can be masked to prevent it from
generating interrupts when its state changes, I/O data logic state can be inverted when
read by the system master.
An open-drain interrupt output pin (INT) allows monitoring of the input pins and is
asserted each time a change occurs in one or several input ports (unless masked).
The Output Enable pin (OE) 3-states any I/O selected as output and can be used as an
input signal to blink or dim LEDs (PWM with frequency > 80 Hz and change duty cycle).
A ‘GPIO All Call’ command allows to program multiple Advanced GPIOs at the same time
even if they have different I2C-bus addresses. This allows optimal code programming
when more than one device needs to be programmed with the same instruction or if all
outputs need to be turned on or off at the same time (for example, LED test).
The Device ID, hard coded in the PCA9698, allows the system master to read
manufacturer, part type and revision information.
The SMBus Alert feature allows the SMBALERT pins of multiple devices with this feature
to be connected together to form a wired-AND signal and to be used in conjunction with
the SMBus Alert Response Address.
The internal Power-On Reset (POR) or hardware reset pin (RESET) initializes the 40 I/Os
as inputs. Three address select pins configure one of 64 slave addresses.
The PCA9698 is available in 56-pin TSSOP and HVQFN packages and is specified over
the 40 °C to +85 °C industrial temperature range.
2. Features
I 1 MHz Fast-mode Plus I2C-bus serial interface
I Compliant with I2C-bus Fast-mode (400 kHz) and Standard-mode (100 kHz)






PCA9698 Datasheet, Funktion
Philips Semiconductors
PCA9698
40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT
terminal 1
index area
IO0_4 1
IO0_5 2
IO0_6 3
VSS 4
IO0_7 5
IO1_0 6
IO1_1 7
IO1_2 8
IO1_3 9
IO1_4 10
VDD 11
IO1_5 12
IO1_6 13
IO1_7 14
PCA9698BS
42 IO4_3
41 IO4_2
40 IO4_1
39 VDD
38 IO4_0
37 IO3_7
36 IO3_6
35 IO3_5
34 IO3_4
33 IO3_3
32 VSS
31 IO3_2
30 IO3_1
29 IO3_0
Transparent top view
Fig 4. Pin configuration for HVQFN56
002aab934
6.2 Pin description
Table 2. Pin description
Symbol
Pin
TSSOP
HVQFN
SDA
1
50
SCL 2
51
IO0_0 to IO0_7 3, 4, 5, 7,
8, 9, 10, 12
52, 53, 54, 56,
1, 2, 3, 5
IO1_0 to IO1_7 13, 14, 15, 16, 6, 7, 8, 9, 10,
17, 19, 20, 21 12, 13, 14
IO2_0 to IO2_7 22, 24, 25, 26, 15, 17, 18, 19,
31, 32, 33, 35 24, 25, 26, 28
IO3_0 to IO3_7 36, 37, 38, 40, 29, 30, 31, 33,
41, 42, 43, 44 34, 35, 36, 37
IO4_0 to IO4_7 45, 47, 48, 49, 38, 40, 41, 42,
50, 52, 53, 54 43, 45, 46, 47
VSS
6, 11, 23,
4, 16, 27, 32,
34, 39, 51
44, 55[1]
VDD
AD0
18, 46
27
11, 39
20
AD1 28 21
Type
input/output
input
input/output
input/output
input/output
input/output
input/output
power supply
power supply
input
input
Description
serial data line
serial clock line
input/output bank 0
input/output bank 1
input/output bank 2
input/output bank 3
input/output bank 4
supply ground
supply voltage
address input 0
address input 1
PCA9698_2
Product data sheet
Rev. 02 — 19 July 2006
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
6 of 47

6 Page









PCA9698 pdf, datenblatt
Philips Semiconductors
PCA9698
40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT
7.4.3 PI0 to PI4 - Polarity Inversion registers
These registers allow inversion of the polarity of the corresponding Input Port register.
Px[y] = 0: The corresponding Input Port register data polarity is retained.
Px[y] = 1: The corresponding Input Port register data polarity is inverted.
Where ‘x’ refers to the bank number (0 to 4); ‘y’ refers to the bit number (0 to 7).
Table 6. PI0 to PI4 - Polarity Inversion registers (address 10h to 14h) bit description
Legend: * default value.
Address Register
Bit
Symbol
Access Value
Description
10h PI0
7 to 0
P0[7:0]
R/W
0000 0000*
Polarity Inversion register bank 0
11h PI1
7 to 0
P1[7:0]
R/W
0000 0000*
Polarity Inversion register bank 1
12h PI2
7 to 0
P2[7:0]
R/W
0000 0000*
Polarity Inversion register bank 2
13h PI3
7 to 0
P3[7:0]
R/W
0000 0000*
Polarity Inversion register bank 3
14h PI4
7 to 0
P4[7:0]
R/W
0000 0000*
Polarity Inversion register bank 4
7.4.4 IOC0 to IOC4 - I/O Configuration registers
These registers configure the direction of the I/O pins.
Cx[y] = 0: The corresponding port pin is an output.
Cx[y] = 1: The corresponding port pin is an input.
Where ‘x’ refers to the bank number (0 to 4); ‘y’ refers to the bit number (0 to 7).
Table 7. IOC0 to IOC4 - I/O Configuration registers (address 18h to 1Ch) bit description
Legend: * default value.
Address Register
Bit
Symbol
Access Value
Description
18h
IOC0
7 to 0
C0[7:0]
R/W
1111 1111*
I/O Configuration register bank 0
19h
IOC1
7 to 0
C1[7:0]
R/W
1111 1111*
I/O Configuration register bank 1
1Ah
IOC2
7 to 0
C2[7:0]
R/W
1111 1111*
I/O Configuration register bank 2
1Bh
IOC3
7 to 0
C3[7:0]
R/W
1111 1111*
I/O Configuration register bank 3
1Ch
IOC4
7 to 0
C4[7:0]
R/W
1111 1111*
I/O Configuration register bank 4
PCA9698_2
Product data sheet
Rev. 02 — 19 July 2006
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
12 of 47

12 Page





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