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PDF AD9246 Data sheet ( Hoja de datos )
| Número de pieza | AD9246 | |
| Descripción | Analog-to-Digital Converter | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de AD9246 (archivo pdf) en la parte inferior de esta página. Total 44 Páginas | ||
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14-Bit, 80 MSPS/105 MSPS/125 MSPS,
1.8 V Analog-to-Digital Converter
AD9246
FEATURES
1.8 V analog supply operation
1.8 V to 3.3 V output supply
SNR = 71.7 dBc (72.7 dBFS) to 70 MHz input
SFDR = 85 dBc to 70 MHz input
Low power: 395 mW @ 125 MSPS
Differential input with 650 MHz bandwidth
On-chip voltage reference and sample-and-hold amplifier
DNL = ±0.4 LSB
Flexible analog input: 1 V p-p to 2 V p-p range
Offset binary, Gray code, or twos complement data format
Clock duty cycle stabilizer
Data output clock
Serial port control
Built-in selectable digital test pattern generation
Programmable clock and data alignment
APPLICATIONS
Ultrasound equipment
IF sampling in communications receivers
IS-95, CDMA-One, IMT-2000
Battery-powered instruments
Hand-held scopemeters
Low cost digital oscilloscopes
GENERAL DESCRIPTION
The AD9246 is a monolithic, single 1.8 V supply, 14-bit, 80 MSPS/
105 MSPS/125 MSPS analog-to-digital converter (ADC), featuring
a high performance sample-and-hold amplifier (SHA) and on-chip
voltage reference. The product uses a multistage differential
pipeline architecture with output error correction logic to
provide 14-bit accuracy at 125 MSPS data rates and guarantees
no missing codes over the full operating temperature range.
The wide bandwidth, truly differential SHA allows a variety of
user-selectable input ranges and offsets, including single-ended
applications. It is suitable for multiplexed systems that switch
full-scale voltage levels in successive channels and for sampling
single-channel inputs at frequencies well beyond the Nyquist rate.
Combined with power and cost savings over previously available
ADCs, the AD9246 is suitable for applications in communications,
imaging, and medical ultrasound.
A differential clock input controls all internal conversion cycles.
A duty cycle stabilizer (DCS) compensates for wide variations in
the clock duty cycle while maintaining excellent overall ADC
performance.
VIN+
VIN–
REFT
REFB
VREF
SENSE
FUNCTIONAL BLOCK DIAGRAM
AVDD
DRVDD
AD9246
SHA
MDAC1
8-STAGE
1 1/2-BIT PIPELINE
A/D
4
A/D
8
3
REF
SELECT
CORRECTION LOGIC
15
OUTPUT BUFFERS
0.5V
CLOCK
DUTY CYCLE
STABILIZER
MODE
SELECT
OR
DCO
D13 (MSB)
D0 (LSB)
SCLK/DFS
SDIO/DCS
CSB
AGND
CLK+ CLK–
Figure 1.
PDWN DRGND
The digital output data is presented in offset binary, Gray code, or
twos complement formats. A data output clock (DCO) is provided
to ensure proper latch timing with receiving logic.
The AD9246 is available in a 48-lead LFCSP_VQ and is specified
over the industrial temperature range (−40°C to +85°C).
PRODUCT HIGHLIGHTS
1. The AD9246 operates from a single 1.8 V power supply
and features a separate digital output driver supply to
accommodate 1.8 V to 3.3 V logic families.
2. The patented SHA input maintains excellent performance
for input frequencies up to 225 MHz.
3. The clock DCS maintains overall ADC performance over a
wide range of clock pulse widths.
4. A standard serial port interface supports various product
features and functions, such as data formatting (offset
binary, twos complement, or Gray coding), enabling the
clock DCS, power-down, and voltage reference mode.
5. The AD9246 is pin-compatible with the AD9233, allowing
a simple migration from 12 bits to 14 bits.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.
1 page  
AD9246
AC SPECIFICATIONS
AVDD = 1.8 V; DRVDD = 2.5 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference;AIN = −1.0 dBFS, DCS
enabled, unless otherwise noted.
Table 2.
Parameter1
SIGNAL-TO-NOISE-RATIO (SNR)
fIN = 2.4 MHz
fIN = 70 MHz
fIN = 100 MHz
fIN = 170 MHz
SIGNAL-TO-NOISE AND DISTORTION
(SINAD)
fIN = 2.4 MHz
fIN = 70 MHz
fIN = 100 MHz
fIN = 170 MHz
EFFECTIVE NUMBER OF BITS (ENOB)
fIN = 2.4 MHz
fIN = 70 MHz
fIN = 100 MHz
fIN = 170 MHz
WORST SECOND OR THIRD HARMONIC
fIN = 2.4 MHz
fIN = 70 MHz
fIN = 100 MHz
fIN = 170 MHz
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
fIN = 2.4 MHz
fIN = 70 MHz
fIN = 100 MHz
fIN = 170 MHz
WORST OTHER HARMONIC OR SPUR
fIN = 2.4 MHz
fIN = 70 MHz
fIN = 100 MHz
fIN = 170 MHz
TWO-TONE SFDR
fIN = 29 MHz (−7 dBFS), 32 MHz
(−7 dBFS)
fIN = 169 MHz (−7 dBFS), 172 MHz
(−7 dBFS)
ANALOG INPUT BANDWIDTH
Temp
25°C
25°C
Full
25°C
25°C
25°C
25°C
Full
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
Full
25°C
25°C
25°C
25°C
Full
25°C
25°C
25°C
25°C
Full
25°C
25°C
25°C
25°C
25°C
AD9246BCPZ-80
Min Typ Max
71.9
71.9
70.8
71.6
70.9
71.1
71.5
70.4
70.6
69.9
11.7
11.6
11.6
11.5
−90
−85
−85
−83.5
−76
90
85
76
85
83.5
−90
−90
−85
−90
−90
87
83
650
AD9246BCPZ-105 AD9246BCPZ-125
Min Typ Max Min Typ Max Unit
71.9
71.9
69.5
71.6
70.9
71.9
71.7
69.5
71.6
70.8
dBc
dBc
dBc
dBc
dBc
71.1
70.8
68.5
70.6
69.9
68.5
11.7
11.6
11.6
11.5
−90
−85
−85
−83.5
−73
90
85
73
85
83.5
73
−90
−90
−80
−90
−90
87
83
650
71.1 dBc
70.6 dBc
dBc
70.6 dBc
69.8 dBc
11.7 Bits
11.6 Bits
11.6 Bits
11.5 Bits
−90 dBc
−85 dBc
−73 dBc
−85 dBc
−83 dBc
90 dBc
85 dBc
dBc
85 dBc
83 dBc
−90 dBc
−90 dBc
−80 dBc
−90 dBc
−90 dBc
85 dBc
84 dBc
650 MHz
1 See AN-835, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions.
Rev. A | Page 5 of 44
5 Page 
AD9246
TYPICAL PERFORMANCE CHARACTERISTICS
AVDD = 1.8 V; DRVDD = 2.5 V; maximum sample rate, DCS enabled, 1 V internal reference; 2 V p-p differential input;
AIN = −1.0 dBFS; 64k sample; TA = 25°C, unless otherwise noted. All figures show typical performance for all speed grades.
00
125MSPS
2.3MHz @ –1dBFS
–20
SNR = 71.9dB (72.9dBFS)
–20
ENOB = 11.7 BITS
SFDR = 90dBc
–40 –40
125MSPS
100.3MHz @ –1dBFS
SNR = 71.6dBc (72.6dBFS)
ENOB = 11.5 BITS
SFDR = 85dBc
–60 –60
–80 –80
–100
–100
–120
–120
–140
0
15.625
31.250
46.875
FREQUENCY (MHz)
62.500
Figure 12. AD9246-125 Single-Tone FFT with fIN = 2.3 MHz
0
125MSPS
30.3MHz @ –1dBFS
–20 SNR = 71.9dBc (72.9dBFS)
ENOB = 11.6 BITS
SFDR = 88.8dBc
–40
–140
0
15.625
31.250
46.875
FREQUENCY (MHz)
62.500
Figure 15. AD9246-125 Single-Tone FFT with fIN = 100.3 MHz
0
125MSPS
140.3MHz @ –1dBFS
–20 SNR = 71dB (72dBFS)
ENOB = 11.4 BITS
SFDR = 85dBc
–40
–60 –60
–80 –80
–100
–100
–120
–120
–140
0
15.625
31.250
46.875
62.500
FREQUENCY (MHz)
Figure 13. AD9246-125 Single-Tone FFT with fIN = 30.3 MHz
0
125MSPS
70.3MHz @ –1dBFS
–20 SNR = 71.7dB (72.7dBFS)
ENOB = 11.5 BITS
SFDR = 85dBc
–40
–140
0
15.625
31.250
46.875
62.500
FREQUENCY (MHz)
Figure 16. AD9246-125 Single-Tone FFT with fIN = 140.3 MHz
0
125MSPS
170.3MHz @ –1dBFS
–20 SNR = 70.8dB (71.8dBFS)
ENOB = 11.4 BITS
SFDR = 83.4dBc
–40
–60 –60
–80 –80
–100
–100
–120
–120
–140
0
15.625
31.250
46.875
62.500
FREQUENCY (MHz)
Figure 14. AD9246-125 Single-Tone FFT with fIN = 70.3 MHz
–140
0
15.625
31.250
46.875
62.500
FREQUENCY (MHz)
Figure 17. AD9246-125 Single-Tone FFT with fIN = 170.3 MHz
Rev. A | Page 11 of 44
11 Page | ||
| Páginas | Total 44 Páginas | |
| PDF Descargar | [ Datasheet AD9246.PDF ] | |
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