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AD9233 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD9233
Beschreibung Analog-to-Digital Converter
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 30 Seiten
AD9233 Datasheet, Funktion
www.DataSheet4U.com
12-Bit, 80 MSPS/105 MSPS/125 MSPS,
1.8 V Analog-to-Digital Converter
AD9233
FEATURES
1.8 V analog supply operation
1.8 V to 3.3 V output supply
SNR = 69.5 dBc (70.5 dBFS) to 70 MHz input
SFDR = 85 dBc to 70 MHz input
Low power: 395 mW @ 125 MSPS
Differential input with 650 MHz bandwidth
On-chip voltage reference and sample-and-hold amplifier
DNL = ±0.15 LSB
Flexible analog input: 1 V p-p to 2 V p-p range
Offset binary, Gray code, or twos complement data format
Clock duty cycle stabilizer
Data output clock
Serial port control
Built-in selectable digital test pattern generation
Programmable clock and data alignment
APPLICATIONS
Ultrasound equipment
IF sampling in communications receivers
IS-95, CDMA-One, IMT-2000
Battery-powered instruments
Hand-held scopemeters
Low cost digital oscilloscopes
GENERAL DESCRIPTION
The AD9233 is a monolithic, single 1.8 V supply, 12-bit, 80 MSPS/
105 MSPS/125 MSPS analog-to-digital converter (ADC), featuring
a high performance sample-and-hold amplifier (SHA) and on-
chip voltage reference. The product uses a multistage differential
pipeline architecture with output error correction logic to
provide 12-bit accuracy at 125 MSPS data rates and guarantees
no missing codes over the full operating temperature range.
The wide bandwidth, truly differential SHA allows a variety of
user-selectable input ranges and offsets, including single-ended
applications. It is suitable for multiplexed systems that switch
full-scale voltage levels in successive channels and for sampling
single-channel inputs at frequencies well beyond the Nyquist rate.
Combined with power and cost savings over previously available
ADCs, the AD9233 is suitable for applications in communications,
imaging, and medical ultrasound.
A differential clock input controls all internal conversion cycles. A
duty cycle stabilizer (DCS) compensates for wide variations in the
clock duty cycle while maintaining excellent overall ADC
performance.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
VIN+
VIN–
REFT
REFB
VREF
SENSE
FUNCTIONAL BLOCK DIAGRAM
AVDD
DRVDD
AD9233
SHA
MDAC1
8-STAGE
1 1/2-BIT PIPELINE
A/D
4
A/D
8
3
CORRECTION LOGIC
13
OUTPUT BUFFERS
REF
SELECT
0.5V
CLOCK
DUTY CYCLE
STABILIZER
MODE
SELECT
OR
DCO
D11 (MSB)
D0 (LSB)
SCLK/DFS
SDIO/DCS
CSB
AGND
CLK+ CLK–
Figure 1.
PDWN DRGND
The digital output data is presented in offset binary, Gray code, or
twos complement formats. A data output clock (DCO) is provided
to ensure proper latch timing with receiving logic.
The AD9233 is available in a 48-lead LFCSP and is specified
over the industrial temperature range (−40°C to +85°C).
PRODUCT HIGHLIGHTS
1. The AD9233 operates from a single 1.8 V power supply
and features a separate digital output driver supply to
accommodate 1.8 V to 3.3 V logic families.
2. The patented SHA input maintains excellent performance
for input frequencies up to 225 MHz.
3. The clock DCS maintains overall ADC performance over a
wide range of clock pulse widths.
4. A standard serial port interface supports various product
features and functions, such as data formatting (offset
binary, twos complement, or Gray coding), enabling the
clock DCS, power-down, and voltage reference mode.
5. The AD9233 is pin compatible with the AD9246, allowing
a simple migration from 12 bits to 14 bits.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.






AD9233 Datasheet, Funktion
AD9233
DIGITAL SPECIFICATIONS
AVDD = 1.8 V; DRVDD = 2.5 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS,
DCS enabled, unless otherwise noted.
Table 3.
Parameter
DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−)
Logic Compliance
Internal Common-Mode Bias
Differential Input Voltage
Input Voltage Range
Input Common-Mode Range
High Level Input Voltage (VIH)
Low Level Input Voltage (VIL)
High Level Input Current (IIH)
Low Level Input Current (IIL)
Input Resistance
Input Capacitance
LOGIC INPUTS (SCLK/DFS, OE, PWDN)
High Level Input Voltage (VIH)
Low Level Input Voltage (VIL)
High Level Input Current (IIH)
Low Level Input Current (IIL)
Input Resistance
Input Capacitance
LOGIC INPUTS (CSB)
High Level Input Voltage (VIH)
Low Level Input Voltage (VIL)
High Level Input Current (IIH)
Low Level Input Current (IIL)
Input Resistance
Input Capacitance
LOGIC INPUTS (SDIO/DCS)
High Level Input Voltage (VIH)
Low Level Input Voltage (VIL)
High Level Input Current (IIH)
Low Level Input Current (IIL)
Input Resistance
Input Capacitance
DIGITAL OUTPUTS
DRVDD = 3.3 V
High Level Output Voltage (VOH, IOH = 50 μA)
High Level Output Voltage (VOH, IOH = 0.5 mA)
Low Level Output Voltage (VOL, IOL = 1.6 mA)
Low Level Output Voltage (VOL, IOL = 50 μA)
DRVDD = 1.8 V
High Level Output Voltage (VOH, IOH = 50 μA)
High Level Output Voltage (VOH, IOH = 0.5 mA)
Low Level Output Voltage (VOL, IOL = 1.6 mA)
Low Level Output Voltage (VOL, IOL = 50 μA)
Temp
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
AD9233BCPZ-80/105/125
Min Typ Max
CMOS/LVDS/LVPECL
1.2
0.2 6
AVDD − 0.3
AVDD + 1.6
1.1 AVDD
1.2 3.6
0 0.8
−10 +10
−10 +10
8 10 12
4
1.2 3.6
0 0.8
−50 −75
−10 +10
30
2
1.2 3.6
0 0.8
−10 +10
+40 +135
26
2
1.2 DRVDD + 0.3
0 0.8
−10 +10
+40 +130
26
5
Full 3.29
Full 3.25
Full
Full
Full 1.79
Full 1.75
Full
Full
0.2
0.05
0.2
0.05
Unit
V
V p-p
V
V
V
V
μA
μA
pF
V
V
μA
μA
pF
V
V
μA
μA
pF
V
V
μA
μA
pF
V
V
V
V
V
V
V
V
Rev. A | Page 6 of 44

6 Page









AD9233 pdf, datenblatt
AD9233
0
125MSPS
225.3MHz @ –1dBFS
–20 SNR = 68.5dBc (69.5dBFS)
ENOB = 11.0 BITS
SFDR = 80.4dBc
–40
–60
–80
–100
–120
–140
0
15.625
31.250
46.875
FREQUENCY (MHz)
62.500
Figure 18. AD9233-125 Single-Tone FFT with FIN = 225.3 MHz
0
125MSPS
300.3MHz @ –1dBFS
–20 SNR = 67.8dBc (68.8dBFS)
ENOB = 10.8 BITS
SFDR = 77.4dBc
–40
–60
–80
–100
–120
–140
0
15.625
31.250
46.875
FREQUENCY (MHz)
62.500
Figure 19. AD9233-125 Single-Tone FFT with FIN = 300.3 MHz
120
SFDR (dBFS)
100
80 SNR (dBFS)
60
40
SFDR (dBc)
20
85dB REFERENCE LINE
SNR (dBc)
0
–90 –80 –70 –60 –50 –40 –30 –20 –10
INPUT AMPLITUDE (dBFS)
0
Figure 20. AD9233 Single-Tone SNR/SFDR vs.
Input Amplitude (AIN) with FIN = 2.4 MHz
100
95
SFDR = –40°C
90
85
SFDR = +25°C
80 SFDR = +85°C
75
SNR = +25°C SNR = –40°C
70
65 SNR = +85°C
60
0
50
100 150
200 250
INPUT FREQUENCY (MHz)
Figure 21. AD9233 Single-Tone SNR/SFDR vs.
Input Frequency (FIN) and Temperature with 2 V p-p Full Scale
100
95
90 SFDR = +85°C
SFDR = +25°C
85
80 SFDR = –40°C
75
70 SNR = +25°C
SNR = –40°C
65
SNR = +85°C
60
0 50
100 150
INPUT FREQUENCY (MHz)
200
250
Figure 22. AD9233 Single-Tone SNR/SFDR vs.
Input Frequency (FIN) and Temperature with 1 V p-p Full Scale
1.0
0.8
OFFSET ERROR
0.5
0.3
0
GAIN ERROR
–0.3
–0.5
–0.8
–1.0
–40
–20
0 20 40
TEMPERATURE (°C)
60
Figure 23. AD9233 Gain and Offset vs. Temperature
80
Rev. A | Page 12 of 44

12 Page





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