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PDF AD9211 Data sheet ( Hoja de datos )
| Número de pieza | AD9211 | |
| Descripción | 1.8 V Analog-to-Digital Converter | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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10-Bit, 200 MSPS/250 MSPS/300 MSPS,
1.8 V Analog-to-Digital Converter
AD9211
FEATURES
SNR = 60.1 dBFS @ fIN up to 70 MHz @ 300 MSPS
ENOB of 9.7 @ fIN up to 70 MHz @ 300 MSPS (−1.0 dBFS)
SFDR = −80 dBc @ fIN up to 70 MHz @ 300 MSPS (−1.0 dBFS)
Excellent linearity
DNL = ±0.1 LSB typical
INL = ±0.2 LSB typical
LVDS at 300 MSPS (ANSI-644 levels)
700 MHz full power analog bandwidth
On-chip reference, no external decoupling required
Integrated input buffer and track-and-hold
Low power dissipation
437 mW @ 300 MSPS—LVDS SDR mode
410 mW @ 300 MSPS—LVDS DDR mode
Programmable input voltage range
1.0 V to 1.5 V, 1.25 V nominal
1.8 V analog and digital supply operation
Selectable output data format (offset binary, twos
complement, Gray code)
Clock duty cycle stabilizer
Integrated data capture clock
APPLICATIONS
Wireless and wired broadband communications
Cable reverse path
Communications test equipment
Radar and satellite subsystems
Power amplifier linearization
GENERAL DESCRIPTION
The AD9211 is a 10-bit monolithic sampling analog-to-digital
converter optimized for high performance, low power, and ease
of use. The product operates at up to a 300 MSPS conversion
rate and is optimized for outstanding dynamic performance
in wideband carrier and broadband systems. All necessary
functions, including a track-and-hold (T/H) and voltage
reference, are included on the chip to provide a complete
signal conversion solution.
The ADC requires a 1.8 V analog voltage supply and a
differential clock for full performance operation. The digital
outputs are LVDS (ANSI-644) compatible and support either
twos complement, offset binary format, or Gray code. A data
clock output is available for proper output data timing.
Fabricated on an advanced CMOS process, the AD9211 is
available in a 56-lead LFCSP, specified over the industrial
temperature range (−40°C to +85°C).
VIN+
VIN–
CLK+
CLK–
FUNCTIONAL BLOCK DIAGRAM
RBIAS PWDN
AGND
AVDD (1.8V)
REFERENCE
AD9211
TRACK-AND-HOLD
CLOCK
MANAGEMENT
ADC 10
10-BIT
CORE
SERIAL PORT
OUTPUT 10
STAGING
LVDS
RESET SCLK SDIO CSB
Figure 1.
DRVDD
DGND
D9 TO D0
OR+
OR–
DCO+
DCO–
PRODUCT HIGHLIGHTS
1. High Performance—Maintains 60.1 dBFS SNR @
300 MSPS with a 70 MHz input.
2. Low Power—Consumes only 410 mW @ 300 MSPS.
3. Ease of Use—LVDS output data and output clock signal
allow interface to current FPGA technology. The on-chip
reference and sample-and-hold provide flexibility in
system design. Use of a single 1.8 V supply simplifies
system power supply design.
4. Serial Port Control—Standard serial port interface
supports various product functions, such as data
formatting, disabling the clock duty cycle stabilizer, power-
down, gain adjust, and output test pattern generation.
5. Pin-Compatible Family—12-bit pin-compatible family
offered as AD9230.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2007 Analog Devices, Inc. All rights reserved.
1 page  
AD9211
AC SPECIFICATIONS1
AVDD = 1.8 V, DRVDD = 1.8 V, TMIN = −40°C, TMAX = +85°C, fIN = −1.0 dBFS, full scale = 1.25 V, DCS enabled, unless otherwise noted.
Table 2.
Parameter2
SNR
fIN = 10 MHz
fIN = 70 MHz
fIN = 170 MHz
SINAD
fIN = 10 MHz
fIN = 70 MHz
fIN = 170 MHz
EFFECTIVE NUMBER OF BITS (ENOB)
fIN = 10 MHz
fIN = 70 MHz
fIN = 170 MHz
WORST HARMONIC (Second or Third)
fIN = 10 MHz
fIN = 70 MHz
fIN = 170 MHz
WORST OTHER
(SFDR Excluding Second and Third)
fIN = 10 MHz
fIN = 70 MHz
fIN = 170 MHz
TWO-TONE IMD
140.2 MHz/141.3 MHz @ −7 dBFS
170.2 MHz/171.3 MHz @ −7 dBFS
ANALOG INPUT BANDWIDTH
Temp
25°C
Full
25°C
Full
25°C
Full
25°C
Full
25°C
Full
25°C
Full
25°C
25°C
25°C
25°C
Full
25°C
Full
25°C
Full
25°C
Full
25°C
Full
25°C
Full
25°C
25°C
25°C
AD9211-200
Min Typ Max
59.0 59.5
58.9
58.9 59.3
58.8
58.5 59.0
58.4
59.0 59.5
58.9
58.8 59.2
58.7
58.2 58.8
58.1
9.8
9.7
9.6
−85 −78
−78
−77 −75
−75
−77 −72
−72
−86 −82
−82
−83 −81
−81
−81 −74
−74
−78
−86
700
AD9211-250
Min Typ Max
58.9 59.4
58.7
58.8 59.3
58.7
58.5 59.0
58.4
58.9 59.4
58.7
58.8 59.2
58.6
58.2 59.0
58.1
9.7
9.7
9.7
−86 −79
−77
−80 −76
−74
−79 −70
−70
−82 −80
−77
−82 −79
−77
−79 −77
−75
−87
−82
700
AD9211-300
Min Typ Max
58.6 59.2
57.5
58.5 59.1
57.0
58.3 58.7
57.0
58.6 59.1
57.3
58.4 59.0
57.0
58.2 58.8
56.7
9.7
9.7
9.6
−80 −75
−70
−80 −74
−67
−80 −73
−67
−82 −75
−70
−80 −75
−71
−80 −75
−70
−81
−82
700
Unit
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
Bits
Bits
Bits
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
MHz
1 All ac specifications tested by driving CLK+ and CLK− differentially.
2 See the AN-835 application note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.
Rev. 0 | Page 4 of 28
5 Page 
AD9211
Pin No.
11
12
13
14
15
16
17
18
19
20
21
22
Mnemonic
D5−
D5+
D6−
D6+
D7−
D7+
D8−
D8+
D9−
D9+
OR−
OR+
Description
D5 Complement Output Bit.
D5 True Output Bit.
D6 Complement Output Bit.
D6 True Output Bit.
D7 Complement Output Bit.
D7 True Output Bit.
D8 Complement Output Bit.
D8 True Output Bit.
D9 Complement Output Bit (MSB).
D9 True Output Bit (MSB).
Overrange Complement Output Bit.
Overrange True Output Bit.
1 AGND and DRGND should be tied to a common quiet ground plane.
Rev. 0 | Page 10 of 28
11 Page | ||
| Páginas | Total 29 Páginas | |
| PDF Descargar | [ Datasheet AD9211.PDF ] | |
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