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PDF AD8382 Data sheet ( Hoja de datos )
| Número de pieza | AD8382 | |
| Descripción | Decimating LCD DecDriver | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Data Sheet
High Performance 12-Bit, 6-Channel
Output, Decimating LCD DecDriver
AD8382
PRODUCT FEATURES
High accuracy, high resolution voltage outputs
12-bit input resolution
Laser trimmed outputs
Fast settling, high voltage drive
33 ns settling time to 0.25% into 200 pF load
Slew rate 390 V/µs
Outputs to within 1.3 V of supply
High update rates
Fast, 120 Ms/s data update rate
Voltage controlled video reference (brightness)and
full-scale (contrast) output levels
Flexible logic
STSQ/XFR allow parallel AD8382 operation
INV bit reverses polarity of video signal
Output overload protection
Low static power dissipation: 743 mW
Includes STBY function
3.3 V logic, 9 V to 18 V analog supplies
Available in 48-lead 7 mm × 7 mm LFCSP
APPLICATIONS
LCD analog column driver
PRODUCT DESCRIPTION
The AD8382 DecDriver® provides a fast, 12-bit latched decimat-
ing digital input that drives six high voltage outputs.12-bit input
words are sequentially loaded into six separate, high speed,
bipolar DACs. A flexible digital input format allows several
AD8382s to be used in parallel for higher resolution displays.
STSQ synchronizes sequential input loading, XFR controls
synchronous output updating, and R/L controls the direction of
loading as either left-to-right or right-to-left. Six channels of
high voltage output drivers drive to within 1.3 V of the rail. The
output signal can be adjusted for dc reference, signal inversion,
and contrast for maximum flexibility.
The AD8382 is fabricated on Analog Devices’ XFHV, fast
bipolar 26 V process, providing fast input logic bipolar DACs
with trimmed accuracy and fast settling, high voltage, precision
drive amplifiers on the same chip. The AD8382 dissipates
743 mW nominal static power. The STBY pin reduces power to
a minimum, with fast recovery.
FUNCTIONAL BLOCK DIAGRAM
DB(0:11)
12
12 12 2-STAGE 12 DAC
LATCH
AD8382
12 2-STAGE 12 DAC
LATCH
STBY
BYP
BIAS
12 2-STAGE 12 DAC
LATCH
12 2-STAGE 12 DAC
LATCH
R/L
E/O
CLK
STSQ
XFR
12 2-STAGE 12 DAC
LATCH
SEQUENCE
CONTROL
12 2-STAGE 12 DAC
LATCH
SCALING
CONTROL
VREFHI VREFLO
INV V1 V2
Figure 1. Functional Block Diagram
VID0
VID1
VID2
VID3
VID4
VID5
Rev. B
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor forany infringements of patents orother
rights of third parties that may result from its use. Specifications subjecttochange withoutnotice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks arethe property of their respectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700©2003–2015 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
AD8382
Data Sheet
Parameter
REFERENCE INPUTS1
V1 Range
V2 Range
V1 Input Current
V2 Input Current
VREFLO Range
VREFHI Range
(VREFHI – VREFLO) Range
VREFHI Input Resistance
VREFLO Bias Current
VREFHI Input Current
VFS Range
POWER SUPPLY
DVCC, Operating Range
DVCC, Quiescent Current
AVCC, Operating Range
Total AVCC Quiescent Current
STBY AVCC Current
STBY DVCC Current
OPERATING TEMPERATURE RANGE
Ambient Temperature Range, TA
Ambient Temperature Range, TA5
Junction Temperature Range, TJ
Conditions
V2 (V1 – 0.25 V)
V2 (V1 – 0.25 V)
VREFHI (VREFLO + 2.75 V)
VREFHI (VREFLO + 2.75 V)
VFS = 2 (VREFHI – VREFLO)
STBY = HIGH
STBY = HIGH
Still Air
100% Tested
Min Typ
5
5
V1 – 0.5
VREFLO
0
0.2
–7.5
20
–0.2
125
3 3.3
23
9
43
0.15
3.5
0
0
25
Max Unit
AVCC – 4
AVCC – 4
AVCC – 1.3
AVCC
2.75
5.5
V
V
A
A
V
V
V
k
A
A
V
3.6 V
31 mA
18 V
52 mA
0.45 mA
5 mA
75 °C
85 °C
125 °C
1 VDE = differential error voltage. VCME = common-mode error voltage. V = maximum deviation between outputs.
Full-scale output voltage = VFS = 2 × (VREFHI – VREFLO). See the Accuracy section on page 14.
2 Measured on two outputs differentially as CLK and DB(0:11) are driven and STSQ and XFR are held LOW.
3 Measured on two outputs differentially as the other four are transitioning by 5 V. Measured for both states of INV.
4 Measured from 50% of falling CLK edge to 50% of output change. Measurement is made for both states of INV.
5 Operation at 85°C ambient temperature requires a thermally optimized PCB layout (see Applications section), minimum airflow of 200 lfm, input clock rate not
exceeding 120 MHz, black-to-white transition ≤ 4 V, and CL ≤ 200 pF.
Rev. B | Page 4 of 21
5 Page 
AD8382
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
0
512 1024 1536 2048 2564 3072 3584 4096
INPUT CODE
Figure 19. Differential Nonlinearity (DNL) vs. Code, INV = LOW
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
0
512 1024 1536 2048 2564 3072 3584 4096
INPUT CODE
Figure 20. Integral Nonlinearity (INL) vs. Code, INV = LOW
3.500
2.625
1.750
0.875
0
–0.875
–1.750
–2.625
–3.500
0
512 1024 1536 2048 2564 3072 3584 4096
INPUT CODE
Figure 21. Common-Mode Error Voltage (VCME) vs. Code
Data Sheet
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
0
512 1024 1536 2048 2564 3072 3584 4096
INPUT CODE
Figure 22. Differential Nonlinearity (DNL) vs. Code, INV = HIGH
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
0
512 1024 1536 2048 2564 3072 3584 4096
INPUT CODE
Figure 23. Integral Nonlinearity (INL) vs. Code, INV = HIGH
5.00
3.75
2.50
1.25
0
–1.25
–2.50
–3.75
–5.00
0
512 1024 1536 2048 2564 3072 3584 4096
INPUT CODE
Figure 24. Differential Error Voltage (VDE) vs. Code
Rev. B | Page 10 of 21
11 Page | ||
| Páginas | Total 22 Páginas | |
| PDF Descargar | [ Datasheet AD8382.PDF ] | |
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