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PDF AD8159 Data sheet ( Hoja de datos )
| Número de pieza | AD8159 | |
| Descripción | Quad Buffer Mux/Demux | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de AD8159 (archivo pdf) en la parte inferior de esta página. Total 25 Páginas | ||
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FEATURES
Port level 2:1 mux/1:2 demux
Each port consists of 4 lanes
Each lane runs from dc to 3.2 Gbps, independent of the other
lanes
Compensates over 40 inches of FR4 at 3.2 Gbps through
2 levels of input equalization or 4 levels of output
pre-emphasis
Accepts ac- or dc-coupled differential CML inputs
Low deterministic jitter, typically 20 ps p-p
Low random jitter, typically 1 ps rms
BER < 10−16
On-chip termination
Reversible inputs and outputs on one port
Unicast or bicast on 1:2 demux function
Port level loopback capability
Single lane switching capability
3.3 V core supply
Flexible I/O supply down to 2.5 V
Low power, typically 1 W in basic configuration
100-lead TQFP_EP
−40°C to +85°C operating temperature range
APPLICATIONS
Low cost redundancy switch
SONET OC-48/SDH-16 and lower data rates
XAUI (10 gigabit Ethernet) over backplane
Gigabit Ethernet over backplane
Fibre Channel 1.06 Gbps and 2.125 Gbps over backplane
InfiniBand® over backplane
PCI Express (PCIe) over backplane
3.2 Gbps
Quad Buffer Mux/Demux
AD8159
FUNCTIONAL BLOCK DIAGRAM
Ix_A[3:0]
RECEIVE
EQUALIZATION
EQ
Ix_B[3:0]
EQ
2:1
TRANSMIT
PRE-
EMPHASIS
I/O
CROSS-
OVER
SWITCH
Ox_C[3:0]/
Ix_C[3:0]
Ox_A[3:0]
Ox_B[3:0]
1:2 EQ
TRANSMIT
PRE-
EMPHASIS
AD8159
QUAD
2:1
MULTIPLEXER/
1:2
DEMULTIPLEXER
RECEIVE
EQUALIZATION
CONTROL
LOGIC
Figure 1.
Ix_C[3:0]/
Ox_C[3:0]
LB_A
LB_B
LB_C
PE_A[1:0]
PE_B[1:0]
PE_C[1:0]
EQ_A
EQ_B
EQ_C
SEL[3:0]
BICAST
REVERSE_C
GENERAL DESCRIPTION
The AD8159 is an asynchronous, protocol agnostic, quad-lane
2:1 switch with 12 differential PECL-/CML-compatible inputs and
12 differential CML outputs. The operation of this product is
optimized for NRZ signaling with data rates of up to 3.2 Gbps
per lane. Each lane offers two levels of input equalization and four
levels of output pre-emphasis.
The AD8159 consists of four multiplexers and four demultiplexers,
one per lane. Each port is a four-lane link, and each lane runs up to
a 3.2 Gbps data rate, independent of the other lanes. The lanes are
switched independently using the four select pins, SEL[3:0]; each
select pin controls one lane of the port. The AD8159 has low
latency and very low lane-to-lane skew.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
The main application of the AD8159 is to support redundancy
on both the backplane side and the line interface side of a serial
link. The device has unicast and bicast capability; therefore, it
can be configured to support either 1 + 1 or 1:1 redundancy.
The AD8159 supports reversing of the output and input pins
on one of its ports, which helps to connect two ASICs with
opposite pinouts.
The AD8159 is also used for testing high speed serial links by
duplicating incoming data and sending it to the destination port
and to the test equipment simultaneously.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2005–2009 Analog Devices, Inc. All rights reserved.
1 page  
AD8159
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
VCC to VEE
VTTI
VTTIO
VTTO
VTTOI
Internal Power Dissipation
Differential Input Voltage
Logic Input Voltage
Storage Temperature Range
Lead Temperature
Rating
3.7 V
VCC + 0.6 V
VCC + 0.6 V
VCC + 0.6 V
VCC + 0.6 V
4.26 W
2.0 V
VEE − 0.3 V < VIN < VCC + 0.6 V
−65°C to +125°C
300°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
Rev. B | Page 4 of 24
5 Page 
AD8159
39.0625ps/DIV
Figure 15. Eye Diagram over Backplane
(42” FR4 + 2 GbX Connectors), PE = 0
39.0625ps/DIV
Figure 18. Eye Diagram over Backplane
(42” FR4 + 2 GbX Connectors), PE = 3
39.0625ps/DIV
Figure 16. Reference Eye Diagram for Figure 19
39.0625ps/DIV
Figure 19. Eye Diagram with Equalization (10” FR4), EQ = 0,
See Figure 32 for Test Circuit Used
39.0625ps/DIV
Figure 17. Reference Eye Diagram for Figure 20
39.0625ps/DIV
Figure 20. Eye Diagram with Equalization (34” FR4 + 2 GbX Connectors),
EQ = 1, See Figure 32 for Test Circuit Used
Rev. B | Page 10 of 24
11 Page | ||
| Páginas | Total 25 Páginas | |
| PDF Descargar | [ Datasheet AD8159.PDF ] | |
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