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AD8045 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD8045
Beschreibung High Speed Op Amp
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 25 Seiten
AD8045 Datasheet, Funktion
Data Sheet
FEATURES
Ultralow distortion
SFDR
−101 dBc at 5 MHz
−90 dBc at 20 MHz
−63 dBc at 70 MHz
Third-order intercept
43 dBm at 10 MHz
Low noise
3 nV/√Hz
3 pA/√Hz
High speed
1 GHz, −3 dB bandwidth (G = +1)
1350 V/µs slew rate
7.5 ns settling time to 0.1%
Standard and low distortion pinout
Supply current: 15 mA
Offset voltage: 1.0 mV max
Wide supply voltage range: 3.3 V to 12 V
APPLICATIONS
Instrumentation
IF and baseband amplifiers
Active filters
ADC drivers
DAC buffers
GENERAL DESCRIPTION
The AD8045 is a unity-gain stable voltage feedback amplifier
with ultralow distortion, low noise, and high slew rate. With a
spurious-free dynamic range of −90 dBc at 20 MHz, the AD8045 is
an ideal solution in a variety of applications, including ultrasound,
automated test equipment (ATE), active filters, and analog-to-
digital converter (ADC) drivers. The Analog Devices, Inc.,
proprietary next generation XFCB process and innovative
architecture enable such high performance amplifiers.
The AD8045 features a low distortion pinout for the LFCSP,
which improves second harmonic distortion and simplifies the
layout of the circuit board.
The AD8045 has a 1 GHz bandwidth, a 1350 V/µs slew rate, and
settles to 0.1% in 7.5 ns. With a wide supply voltage range (3.3 V
to 12 V) and a low offset voltage (200 µV), the AD8045 is an
ideal candidate for systems that require high dynamic range,
precision, and high speed.
The AD8045 amplifier is available in a 3 mm × 3 mm LFCSP
and the standard 8-lead SOIC. Both packages feature an exposed
Rev. B
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
3 nV/√Hz, Ultralow Distortion,
High Speed Op Amp
AD8045
CONNECTION DIAGRAMS
AD8045
TOP VIEW
(Not to Scale)
NIC 1
FEEDBACK 2
8 +VS
7 OUTPUT
–IN 3
6 NIC
+IN 4
5 –VS
NOTES
1. NIC = NO INTERNAL CONNECTION.
Figure 1. 8-Lead AD8045 LFCSP (CP-8)
AD8045
TOP VIEW
(Not to Scale)
FEEDBACK 1
–IN 2
+IN 3
–VS 4
8 NIC
7 +VS
6 OUTPUT
5 NIC
NOTES
1. NIC = NO INTERNAL CONNECTION.
Figure 2. 8-Lead AD8045 SOIC/EP (RD-8)
paddle that provides a low thermal resistance path to the
printed circuit board (PCB). This enables more efficient heat
transfer and increases reliability. The AD8045 works over the
extended industrial temperature range (−40°C to +125°C).
–20
G = +1
–30 VS = ±5V
VOUT = 2V p-p
–40 RL = 1k
RS = 100
–50
–60
–70
–80
–90
–100
HD3 LFCSP
HD2 LFCSP
–110
–120
0.1 1 10 100
FREQUENCY (MHz)
Figure 3. Harmonic Distortion vs. Frequency for Various Packages
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2004–2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com






AD8045 Datasheet, Funktion
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter
Supply Voltage
Power Dissipation
Common-Mode Input Voltage
Differential Input Voltage
Exposed Paddle Voltage
Storage Temperature Range
Operating Temperature Range
Lead Temperature (Soldering 10 sec)
Junction Temperature
Rating
12.6 V
See Figure 4
−VS − 0.7 V to +VS + 0.7 V
±VS
−VS
−65°C to +125°C
−40°C to +125°C
300°C
150°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions; that is, θJA is specified
for the device soldered in the circuit board for surface-mount
packages.
Table 4. Thermal Resistance
Package Type
θJA θJC Unit
SOIC
80 30 °C/W
LFCSP
93 35 °C/W
Maximum Power Dissipation
The maximum safe power dissipation for the AD8045 is limited
by the associated rise in junction temperature (TJ) on the die. At
approximately 150°C, which is the glass transition temperature,
the properties of the plastic change. Even temporarily exceeding
this temperature limit may change the stresses that the package
exerts on the die, permanently shifting the parametric performance
of the AD8045. Exceeding a junction temperature of 175°C for
an extended period of time can result in changes in silicon devices,
potentially causing degradation or loss of functionality.
The power dissipated in the package (PD) is the sum of the
quiescent power dissipation and the power dissipated in the
die due to the AD8045 drive at the output. The quiescent
power is the voltage between the supply pins (VS) times the
quiescent current (IS).
AD8045
PD = Quiescent Power + (Total Drive Power Load Power)
( )PD = VS × I S
+

VS
2
×
VOUT
RL

VOUT
RL
2
RMS output voltages should be considered. If RL is referenced
to −VS, as in single-supply operation, the total drive power is
VS × IOUT. If the rms signal levels are indeterminate, consider
the worst case, when VOUT = VS/4 for RL to midsupply.
PD
= (VS
×IS )+
(VS / 4)2
RL
In single-supply operation with RL referenced to −VS, worst case
is VOUT = VS/2.
Airflow increases heat dissipation, effectively reducing θJA. Also,
more metal directly in contact with the package leads and exposed
paddle from metal traces, through holes, ground, and power
planes reduces θJA.
Figure 4 shows the maximum safe power dissipation in the
package vs. the ambient temperature for the exposed paddle
SOIC (80°C/W) and LFCSP (93°C/W) package on a JEDEC
standard 4-layer board. θJA values are approximations.
4.0
3.5
3.0
2.5
2.0
1.5
SOIC
1.0
LFCSP
0.5
0.0
–40 –20
0
20 40 60 80 100 120
AMBIENT TEMPERATURE (°C)
Figure 4. Maximum Power Dissipation vs. Temperature for a 4-Layer Board
ESD CAUTION
Rev. B | Page 5 of 24

6 Page









AD8045 pdf, datenblatt
Data Sheet
–40
G = +1
VS = +5V
–50 RL = 1k
RS = 100
f = 10MHz
–60
–70
HD3 SOIC AND LFCSP
–80
–90
HD2 SOIC
–100
HD2 LFCSP
–110
0.5
1.0 1.5 2.0 2.5
OUTPUT VOLTAGE (V p-p)
3.0
Figure 31. Harmonic Distortion vs. Output Voltage for Various Packages
–40
G = +1
VS = +5V
–50 RL = 150
RS = 100
f = 10MHz
–60
–70
HD3 SOIC AND LFCSP
–80
–90
–100
HD2 SOIC
HD2 LFCSP
–110
0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 2.5
OUTPUT VOLTAGE (V p-p)
Figure 32. Harmonic Distortion vs. Output Voltage for Various Packages
1600
RL = 1k
1400 VS = ±5V
POSITIVE SLEW RATE
1200
1000
NEGATIVE SLEW RATE
800
600
400
200
0
01234
OUTPUT VOLTAGE STEP (V)
Figure 33. Slew Rate vs. Output Voltage
5
AD8045
0.15
0.10
RS = 100
RL = 150
G = +1
VS = ±2.5
OR VS = ±5V
0.05
0
–0.05
–0.10
–0.15
0
5 10 15 20 25
TIME (ns)
Figure 34. Small Signal Transient Response for Various Supplies and Loads
0.15
0.10
RL = 1k
CL = 10pF
RSNUB = 30
VS = ±5V
G = +1
0.05
0
–0.05
–0.10
RSNUB
30
CL
10pF
RL
1k
–0.15
0
5 10 15 20 25
TIME (ns)
Figure 35. Small Signal Transient Response for Various Supplies and Loads
0.15
0.10
0.05
VS = ±2.5V
G = +2
RC = 1k
OR RC = 150k
0
–0.05
–0.10
–0.15
0
5 10 15 20 25
TIME (ns)
Figure 36. Small Signal Transient Response for Various Loads
Rev. B | Page 11 of 24

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