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AD7796 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD7796
Beschreibung (AD7796 / AD7797) Sigma-Delta ADC
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 24 Seiten
AD7796 Datasheet, Funktion
www.DataSheet4U.com
Low Power, 16-/24-Bit Sigma-Delta ADC
for Bridge Sensors
AD7796/AD7797
FEATURES
RMS noise: 65 nV
Instrumentation amp
Temperature sensor
Internal clock oscillator
Simultaneous 50 Hz/60 Hz rejection
Update rate: 4.17 Hz to 123 Hz
Current: 250 μA typ
Power-down: 1 μA
Power supply: 2.7 V to 5.25 V
–40°C to +85°C temperature range
Independent interface power supply
16-lead TSSOP
INTERFACE
3-wire serial
SPI®, QSPI™, MICROWIRE™, and DSP compatible
Schmitt trigger on SCLK
GENERAL DESCRIPTION
The AD7796/AD7797 are complete, analog front ends for high
precision, bridge sensor applications such as weigh scales. The
AD7796/AD7797 contain a Σ-Δ ADC capable of 16-/24-bit
resolution, respectively. The on-chip instrumentation amplifier
has a fixed gain of 128, allowing small amplitude signals such as
those from bridge sensors to be directly interfaced to the ADC.
Each part has one differential input and contains a temperature
sensor that is internally connected to the ADC. This sensor can
be used to perform temperature compensation of the bridge.
The devices can be operated with the internal clock or an
external clock. The output data rate from the parts is software-
programmable and can be varied from 4.17 Hz to 123 Hz.
The AD7796/AD7797 operate with a power supply from 2.7 V
to 5.25 V. Each part consumes a current of 250 μA typical and is
housed in a 16-lead TSSOP.
APPLICATIONS
Weigh scales
Strain gages
Industrial process control
Instrumentation
Portable instrumentation
AIN(+)
AIN(–)
FUNCTIONAL BLOCK DIAGRAM
GND AVDD
REFIN(+) REFIN(–)
AVDD
AD7796: 16-BIT ADC
AD7797: 24-BIT ADC
MUX
×128
Σ-Δ
ADC
SERIAL
INTERFACE
AND
CONTROL
LOGIC
DOUT/RDY
DIN
SCLK
CS
GND
AD7796/
AD7797
REFERENCE
TEMP
SENSOR
INTERNAL
CLOCK
Figure 1.
CLK
DVDD
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.






AD7796 Datasheet, Funktion
AD7796/AD7797
TIMING DIAGRAMS
CS (I)
DOUT/RDY (O)
SCLK (I)
t1
t2
MSB
t3
t6
LSB
t7
t5
I = INPUT, O = OUTPUT
t4
Figure 3. Read Cycle Timing Diagram
CS (I)
t8 t11
SCLK (I)
DIN (I)
t9
t10
MSB
LSB
I = INPUT
Figure 4. Write Cycle Timing Diagram
Rev. A | Page 6 of 24

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AD7796 pdf, datenblatt
AD7796/AD7797
STATUS REGISTER
RS2, RS1, RS0 = 0, 0, 0; Power-On/Reset = 0x80
The status register is an 8-bit read-only register. To access the ADC status register, the user must write to the communication register,
select the next operation to be a read, and load Bit RS2, Bit RS1, and Bit RS0 with 0. Table 11 outlines the bit designations for the status
register. SR0 through SR7 indicate the bit locations, with SR denoting that the bits are in the status register. SR7 denotes the first bit of the
data stream. The number in brackets indicates the power-on/reset default status of that bit.
MSB LSB
SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0
RDY(1)
ERR(0)
0(0)
0(0)
0(0)
CH2(0)
CH1(0)
CH0(0)
Table 11. Status Register Bit Designations
Bit Location Bit Name Description
SR7 RDY Ready Bit for ADC. Cleared when data is written to the ADC data register. Set automatically after the ADC data
register has been read or before the data register is updated with a new conversion result to indicate to the
user not to read the conversion data. It is also set when the part is placed in power-down mode. DOUT/RDY
also indicates the end of a conversion and can be used as an alternative to the status register for monitoring
the ADC for conversion data.
SR6 ERR ADC Error Bit. This bit is written to at the same time as the RDY bit. Set to indicate that the result written to the
ADC data register has been clamped to all 0s or all 1s. Error sources include overrange and underrange.
Cleared by a write operation to start a conversion.
SR5 to SR3 0
These bits are automatically cleared.
SR2 to SR0 CH2 to CH0 These bits indicate the channel that is being converted by the ADC.
MODE REGISTER
RS2, RS1, RS0 = 0, 0, 1; Power-On/Reset = 0x000A
The mode register is a 16-bit read/write register. This register is used to select the operating mode, update rate, and clock source. Table 12
outlines the bit designations for this register. MR0 through MR15 indicate the bit locations, with MR denoting that the bits are in the
mode register. MR15 denotes the first bit of the data stream. The number in brackets indicates the power-on/reset default status of that
bit. Any write to the setup register resets the modulator and filter, and sets the RDY bit.
MSB
MR15
MD2(0)
MR14
MD1(0)
MR13
MD0(0)
MR12
0(0)
MR11
0(0)
MR10
0(0)
MR9
0(0)
MR8
0(0)
MR7
CLK1(0)
MR6
CLK0(0)
MR5
0(0)
MR4
0(0)
MR3
FS3(1)
MR2
FS2(0)
MR1
FS1(1)
LSB
MR0
FS0(0)
Table 12. Mode Register Bit Designations
Bit Location Bit Name Description
MR15 to MR13 MD2 to MD0 Mode Select Bits. These bits select the operational mode of the AD7796/AD7797 (see Table 13).
MR12 to MR8 0
These bits must be programmed with a Logic 0 for correct operation.
MR7 to MR6
CLK1 to CLK0
These bits are used to select the clock source for the AD7796/AD7797. Either an on-chip 64 kHz clock
or an external clock can be used. The ability to override using an external clock allows several AD7796/
AD7797 devices to be synchronized. In addition, 50 Hz/60 Hz rejection is improved when an accurate
external clock drives the AD7796/AD7797.
CLK1 CLK0 ADC Clock Source
0 0 Internal 64 kHz Clock. Internal clock is not available at the CLK pin.
0 1 Internal 64 kHz Clock. This clock is made available at the CLK pin.
1 0 External 64 kHz Clock Used. An external clock gives better 50 Hz/60 Hz rejection.
See Table 1 for the external clock specifications.
1 1 External Clock Used. The external clock is divided by 2 within the AD7796/AD7797.
MR5 to MR4 0
These bits must be programmed with a Logic 0 for correct operation.
MR3 to MR0 FS3 to FS0 Filter Update Rate Select Bits (see Table 14).
Rev. A | Page 12 of 24

12 Page





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