ADSP-21362 Datasheet PDF - Analog Devices
| Part Number | ADSP-21362 | |
| Description | (ADSP-21362 - ADSP-21366) SHARC Processor | |
| Manufacturers | Analog Devices | |
| Logo |  |
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SHARC® Processor
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
SUMMARY
High performance, 32-bit/40-bit, floating-point processor
optimized for high performance processing
Single-instruction, multiple-data (SIMD) computational
architecture
On-chip memory—3M bit of on-chip SRAM
Code compatible with all other members of the SHARC family
The ADSP-2136x processors are available with a 333 MHz
core instruction rate and unique peripherals such as the digi-
tal audio interface, S/PDIF transceiver, DTCP (digital
transmission content protection protocol), serial ports,
8-channel asynchronous sample rate converter, precision
clock generators, and more. For complete ordering informa-
tion, see Ordering Guide on Page 52.
CORE PROCESSOR
TIMER
INSTRUCTION
CACHE
32-BIT ؋ 48-BIT
DAG1
8؋4؋32
DAG2
8؋4؋32
PROGRAM
SEQUENCER
BLOCK 0
SRAM
1M BIT ROM
2M BIT
4 BLOCKS OF ON-CHIP MEMORY
BLOCK 1
BLOCK 2
SRAM
1M BIT ROM
2M BIT
SRAM
0.5M BIT
BLOCK 3
SRAM
0.5M BIT
ADDR DATA
ADDR DATA ADDR DATA ADDR DATA
PM ADDRESS BUS
32
DM ADDRESS BUS 32
PM DATA BUS
64
DM DATA BUS 64
PROCESSING
ELEMENT
(PEX)
PROCESSING
ELEMENT
(PEY)
PX REGISTER
JTAG TEST AND EMULATION
6
S
IOA IOD
IOA IOD
IOA IOD
IOP REGISTERS
(MEMORY MAPPED)
SPI
SPORTS
IDP
PCG
TIMERS
SRC
SPDIF
DTCP
I/O PROCESSOR
AND PERIPHERALS
IOA IOD
SIGNAL
ROUTING
UNIT
Figure 1. Functional Block Diagram—Processor Core
SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.
Tel : 781.329.4700
www.analog.com
Fax: 781.461.3113 © 2006 Analog Devices, Inc. All rights reserved.
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ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
C LOC K
2
2
3
A DC
(OPTI ONA L)
C LK
FS
S D AT
D AC
(OPTI ONA L)
C LK
FS
S D AT
A D SP-2 1 3 6 x
C LK IN
X TA L
C LK _C FG1-0
B OOTC FG1 -0
FLA G3-1
CLK OU T
ALE
AD 1 5-0
RD
WR
FLAG0
D A I_P1
DA I_ P2
DA I_ P3
D A I_P 18
D AI _P 19
DA I_ P2 0
SR U
S C LK 0
S FS0
S D 0A
S D 0B
SP OR T0-5
TIME R S
SPD IF
SR C
ID P
S PI
DA I
RES ET
CLK
FS
PC GA
P CG B
JTA G
6
LA TCH
A DD R
D ATA
OE
WE
CS
PA R A L L EL
POR T
RAM
I /O D EVI CE
Figure 2. ADSP-2136x System Sample Configuration
SHARC FAMILY CORE ARCHITECTURE
The ADSP-2136x is code-compatible at the assembly level with
the ADSP-2126x, ADSP-21160, and ADSP-21161, and with the
first generation ADSP-2106x SHARC processors. The
ADSP-2136x shares architectural features with the ADSP-2126x
and ADSP-2116x SIMD SHARC processors, as detailed in the
following sections.
SIMD Computational Engine
The ADSP-2136x contains two computational processing ele-
ments that operate as a single-instruction multiple-data (SIMD)
engine. The processing elements are referred to as PEX and PEY
and each contains an ALU, multiplier, shifter, and register file.
PEX is always active, and PEY may be enabled by setting the
PEYEN mode bit in the MODE1 register. When this mode is
enabled, the same instruction is executed in both processing ele-
ments, but each processing element operates on different data.
This architecture is efficient at executing math intensive signal
processing algorithms.
Entering SIMD mode also has an effect on the way data is trans-
ferred between memory and the processing elements. When in
SIMD mode, twice the data bandwidth is required to sustain
computational operation in the processing elements. Because of
this requirement, entering SIMD mode also doubles the
bandwidth between memory and the processing elements.
When using the DAGs to transfer data in SIMD mode, two data
values are transferred with each access of memory or the regis-
ter file.
Independent, Parallel Computation Units
Within each processing element is a set of computational units.
The computational units consist of an arithmetic/logic unit
(ALU), multiplier, and shifter. These units perform all opera-
tions in a single cycle. The three units within each processing
element are arranged in parallel, maximizing computational
throughput. Single multifunction instructions execute parallel
ALU and multiplier operations. In SIMD mode, the parallel
ALU and multiplier operations occur in both processing
elements. These computation units support IEEE 32-bit
single-precision floating-point, 40-bit extended-precision
floating-point, and 32-bit fixed-point data formats.
Data Register File
A general-purpose data register file is contained in each pro-
cessing element. The register files transfer data between the
computation units and the data buses, and store intermediate
results. These 10-port, 32-register (16 primary, 16 secondary)
register files, combined with the ADSP-2136x enhanced
Rev. A | Page 5 of 52 | December 2006
Preview 5 Page |
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| Information | Total 30 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ ADSP-21362.PDF Datasheet ] | |
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