PDF AD7765 Data sheet ( Hoja de datos )

Número de pieza	AD7765
Descripción	112dB ADC
Fabricantes	Analog Devices
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No Preview Available ! www.DataSheet4U.com Preliminary Technical Data 24-Bit, 156 kSPS,112dB Σ∆ ADC, With On-Chip Buffers, Serial Interface AD7765 FEATURES High performance 24-bit Sigma-Delta ADC 112dB SNR at 78kHz output data rate 109dB SNR at 156 kHz output data rate 156 kHz maximum fully filtered output word rate Pin-selectable over-sampling rate (128x & 256x) Flexible SPI serial interface Fully differential modulator input On-chip differential amplifier for signal buffering On-chip Reference Buffer Low pass FIR filter Over-range alert pin Digital gain correction registers Power down mode Synchronization of multiple devices via SYNC pin Daisy Chaining FUNCTIONAL BLOCK DIAGRAM VOUTA- VOUTA+ VIN+ VIN- MCLK VINA+ VINA- VREF+ REFGND SYNC RESET/PWRDN DIFF + B_ UF AD7765 Interface Logic and Offset & Gain Correction Registers Multi-Bit Sigma-Delta Modulator Reconstruction Decimation FIR Filter Engine AVDD1 AVDD2 AVDD3 AVDD4 DVDD OVERRANGE DECAP RBIAS Figure 1. APPLICATIONS Data acquisition systems Vibration analysis Instrumentation PRODUCT OVERVIEW The AD7765 high performance, 24-bit, sigma delta analog to digital converter combines wide input bandwidth, high speed and performance of 112dB at a 156Khz output data rate with the benefits of sigma delta conversion, while, also offering excellent DC specifications which make the converter ideal for high speed data acquisition of AC signals where DC data is also a requirement. A wide dynamic range combined with significantly reduced anti-aliasing requirements simplifies the design process. The AD7765 offers pin-selectable decimation rates of 128x and 256x. Other features include an integrated buffer to drive the reference, a differential amplifier for signal buffering and level shifting. The addition of an internal gain register, an over-range alert pin, and a low-pass digital FIR filter make the AD7765 a compact highly integrated data acquisition device requiring minimal peripheral component selection. The AD7765 is ideally suited to applications demanding high SNR without necessitating design of complex front end signal processing. The differential input is sampled at up to 40MS/s by an analog modulator. The modulator output is processed by a series of low-pass filters. The sample rate, filter corner frequencies and output word rate are determined by the external clock frequency supplied to the AD7765. The reference voltage supplied to the AD7765 determines the analog input range. With a 4V reference, the analog input range is ±3.2V differential biased around a common mode of 2V. This common mode biasing can be achieved using the on-chip differential amplifiers, further reducing the external signal conditioning requirements. The AD7765 is available in a 28-lead TSSOP package and is specified over the industrial temperature range from -40°C to +85°C RELATED DEVICES Part no. AD7760 AD7762 AD7763 AD7764 Description 24-bit, 2.5MSPS, 100dB Σ∆, parallel interface 24-bit, 625ksps, 109dB Σ∆, parallel interface 24-bit, 625ksps, 109dB Σ∆, serial interface 24-bit, 312kSPS, 109dB Σ∆, serial interface Rev. PrC Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved. 1 page Preliminary Technical Data TIMING SPECIFICATIONS Table 2.AVDD1 = DVDD = 2.5 V, AVDD2 = AVDD3 = AVDD4 = 5 V, VREF = 4.096 V, TA = +25°C, CLOAD = 25pF. Parameter fMCLK fICLK t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t121 t13 t14 t15 t16 Limit at TMIN, TMAX 500 40 250 20 1 × tICLK 1 × tICLK TBD TBD TBD TBD TBD TBD TBD TBD × tSCO TBD TBD TBD TBD TBD TBD Unit KHz min MHz max kHz min MHz max typ typ typ typ ns max ns min ns max typ typ max min max min min max min Description Applied Master Clock Frequency Internal Modulator Clock Derived from MCLK. SCO High Period SCO Low Period SCO rising edge to FSO falling edge Data Access time, FSO falling edge to data active Initial Data Access Time, SDO active to SDO valid SDO valid to SCO Rising Edge SCO rising edge to SDO valid SCO rising edge to FSO rising edge FSO rising edge to SDO invalid FSO Low Period FSI Low Period FSI Low Period SCO rising edge to SDI valid SDI valid to SCO rising edge SCO rising edge to SDI valid FSI rising edge to SDI three-state 1 This is the max time FSI can be held low when writing to an individual (non-daisy chained) AD7764 device. AD7765 Rev. PrC \| Page 5 of 21 5 Page Preliminary Technical Data TYPICAL PERFORMANCE CHARACTERISTICS AD7765 Figure 6 Figure 9 Figure 7 Figure 10 Figure 8 Rev. PrC \| Page 11 of 21 Figure 11 11 Page

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