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PDF AD5934 Data sheet ( Hoja de datos )
| Número de pieza | AD5934 | |
| Descripción | 12-Bit Impedance Converter | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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250 kSPS, 12-Bit Impedance Converter,
Network Analyzer
AD5934
FEATURES
Programmable output peak-to-peak excitation voltage
to a max frequency of 100 kHz
Programmable frequency sweep capability with
serial I2C® interface
Frequency resolution of 27 bits (<0.1 Hz)
Impedance measurement range from 100 Ω to 10 MΩ
Phase measurement capability
System accuracy of 0.5%
2.7 V to 5.5 V power supply operation
Temperature range −40°C to +125°C
16-lead SSOP package
APPLICATIONS
Electrochemical analysis
Bioelectrical impedance analysis
Impedance spectroscopy
Complex impedance measurement
Corrosion monitoring and protection equipment
Biomedical and automotive sensors
Proximity sensing
Nondestructive testing
Material property analysis
Fuel/battery cell condition monitoring
GENERAL DESCRIPTION
The AD5934 is a high precision impedance converter system
solution which combines an on-board frequency generator with
a 12-bit, 250 kSPS, analog-to-digital converter (ADC). The
frequency generator allows an external complex impedance to
be excited with a known frequency. The response signal from
the impedance is sampled by the on-board ADC and a discrete
Fourier transform (DFT) is processed by an on-board DSP
engine. The DFT algorithm returns a real (R) and imaginary (I)
data-word at each output frequency.
The magnitude of the impedance and relative phase of the
impedance at each frequency point along the sweep is easily
calculated using the following two equations:
Magnitude = R2 + I2
Phase = Tan−1(I / R)
Table 1. Related Devices
Part No. Description
AD5933 2.7 V to 5.5 V. 1 MSPS, 12-bit impedance, with
internal temperature sensor, 16-lead SSOP.
FUNCTIONAL BLOCK DIAGRAM
MCLK
AVDD
DVDD
SCL
SDA
I2C
INTERFACE
REAL IMAGINARY
REGISTER REGISTER
1024-POINT DFT
DDS
CORE
(27 BITS)
DAC
AD5934
ROUT
VOUT
Z(ω)
RFB
ADC
(12 BITS)
GAIN
LPF
AGND DGND
Figure 1.
VIN
VDD/2
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved.
1 page  
AD5934
I2C SERIAL INTERFACE TIMING CHARACTERISTICS
VDD = 2.7 V to 5.5 V. All specifications TMIN to TMAX, unless otherwise noted.1
Table 3.
Parameter2
FSCL
t1
t2
t3
t4
t5
t6 3
t7
t8
t9
t10
t11
CB
Limit at TMIN, TMAX
400
2. 5
0. 6
1. 3
0. 6
100
0. 9
0
0. 6
0. 6
1. 3
300
0
300
0
250
20 + 0.1 CB4
400
Unit
kHz max
μs min
μs min
μs min
μs min
ns min
μs max
μs min
μs min
μs min
μs min
ns max
ns min
ns max
ns min
ns max
ns min
pF max
Description
SCL clock frequency
SCL cycle time
tHIGH, SCL high time
tLOW, SCL low time
tHD, STA, start/repeated start condition hold time
tSU, DAT, data setup time
tHD, DAT, data hold time
tHD, DAT, data hold time
tSU, STA, setup time for repeated start
tSU, STO, stop condition setup time
tBUF, bus free time between a stop and a start condition
tF, rise time of SDA when transmitting
tR, rise time of SCL and SDA when receiving (CMOS compatible)
tF, fall time of SCL and SDA when transmitting
tF, fall time of SDA when receiving (CMOS compatible)
tF, fall time of SDA when receiving
tF, fall time of SCL and SDA when transmitting
Capacitive load for each bus line
1 See Figure 2.
2 Guaranteed by design and characterization, not production tested.
3 A master device must provide a hold time of at least 300 ns for the SDA signal (referred to VIH MIN of the SCL signal) in order to bridge the undefined SCL’s falling edge.
4 CB is the total capacitance of one bus line in pF. Note that tR and tF are measured between 0.3 VDD and 0.7 VDD.
SDA
t9
t3 t10 t11
t4
SCL
t4
t6 t2
t5 t7
t1
START
CONDITION
REPEATED
START
CONDITION
Figure 2. I2C Interface Timing Diagram
t8
STOP
CONDITION
Rev. 0 | Page 5 of 32
5 Page 
SYSTEM DESCRIPTION
MCLK
AD5934
MICROCONTROLLER
SCL
SDA
I2C
INTERFACE
DDS
CORE
(27 BITS)
COS SIN
DAC
REAL IMAGINARY
REGISTER REGISTER
AD5934
MAC CORE
(1024 DFT)
WINDOWING
OF DATA
MCLK
ADC
(12 BITS)
PROGRAMMABLE
GAIN AMPLIFIER
X5
LPF X1
ROUT
VOUT
Z(ω)
RFB
VIN
VDD/2
Figure 14. AD5934 Block Overview
The AD5934 is a high precision impedance converter system
solution which combines an on-board frequency generator with a
12-bit, 250 kSPS ADC. The frequency generator allows an external
complex impedance to be excited with a known frequency. The
response signal from the impedance is sampled by the on-board
ADC and DFT processed by an on-board DSP engine. The DFT
algorithm returns both a real (R) and imaginary (I) data-word at
each frequency point along the sweep. The impedance magnitude
and phase is easily calculated using the following equations:
Magnitude = R2 + I 2
Phase = Tan−1(I / R)
To characterize an impedance profile Z(ω), generally a frequency
sweep is required like that shown in Figure 15.
The AD5934 permits the user to perform a frequency sweep with
a user-defined start frequency, frequency resolution, and number
of points in the sweep. In addition, the device allows the user to
program the peak-to-peak value of the output sinusoidal signal as
an excitation to the external unknown impedance connected
between the VOUT and VIN pins.
Table 6 gives the four possible output peak-to-peak voltages and
the corresponding dc bias levels for each range.
Table 6.
Output Excitation Voltage Amplitude
Range 1: 1.98 V p-p
Range 2: 0.99 V p-p
Range 3: 383 mV p-p
Range 4: 198 mV p-p
Output DC Bias Level
1.48 V
0.74V
0.31 V
0.179 V
The excitation signal for the transmit stage is provided on-chip
using DDS techniques which permit subhertz resolution. The
receive stage receives the input signal current from the unknown
impedance, performs signal processing, and digitizes the result.
The clock for the DDS is generated from an external reference
clock which is provided by the user at MCLK.
FREQUENCY
Figure 15.
Rev. 0 | Page 11 of 32
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD5934.PDF ] | |
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