|
|
PDF AD15452 Data sheet ( Hoja de datos )
| Número de pieza | AD15452 | |
| Descripción | 12-Bit 65 MSPS Quad A/D Converter | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de AD15452 (archivo pdf) en la parte inferior de esta página. Total 16 Páginas | ||
|
No Preview Available !
www.DataSheet4U.com
12-Bit 65 MSPS Quad A/D Converter with
Integrated Signal Conditioning
AD15452
FEATURES
12-bit, 65 MSPS, quad, analog-to-digital converter
Differential input with 100 Ω input impedance
Full-scale analog input: 296 mV p-p
200 MHz, 3 dB bandwidth
SNR @ −9 dBFS
64 dBFS (70 MHz AIN)
64 dBFS (140 MHz AIN)
SFDR @ −9 dBFS
81 dBFS (70 MHz AIN)
73 dBFS (140 MHz AIN)
475 mW per channel
Quad LVDS outputs
Data clock output provided
Offset binary output data format
APPLICATIONS
Antijam GPS receivers
Wireless and wired broadband communications
Communications test equipment
PRODUCT HIGHLIGHTS
1. Quad, 12-bit, 65 MSPS, analog-to-digital converter with
integrated analog signal conditioning optimized for antijam
global positioning system receiver (AJ-GPS) applications.
2. Packaged in a space saving 81-lead, 10 mm x 10 mm chip
scale package ball grid array (CSP_BGA) and specified over
the industrial temperature range (−40°C to +85°C).
GENERAL DESCRIPTION
The AD15452 is a quad, 12-bit, 65 MSPS, analog-to-digital
converter (ADC). It features a differential front-end
amplification circuit followed by a sample-and-hold amplifier
and multistage pipeline analog-to-digital converter. It is
designed to operate with a 3.3 V analog supply and a 3.3 V
digital supply. Each input is fully differential. The input signals
are ac-coupled and terminated in 100 Ω input impedances. The
full-scale differential signal input range is 296 mV p-p.
Four separate 12-bit digital output signals provide data flow
from the ADCs. The digital output data is presented in offset
binary format. A single-ended clock input is used to control all
internal conversion cycles. The AD15452 is optimized for
applications in antijam global positioning receivers and is suited
for communications applications.
FUNCTIONAL BLOCK DIAGRAM
IN_A
D+A D+C
LPF D–A D–C LPF
IN_C
PDOWN
CLK
IN_B
D+B D+D
LPF D–B D–D LPF
Figure 1.
IN_D
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
© 2005 Analog Devices, Inc. All rights reserved.
1 page  
AD15452
Table 2. Test Levels
Test
Level
Description
I 100% production tested.
II 100% production tested at 25°C, and sample tested at specified temperatures.
III Sample tested only.
IV Parameter is guaranteed by design and characterization testing.
V Parameter is a typical value only.
VI All devices are 100% production tested at 25°C, guaranteed by design and characterization testing for industrial temperature
range, 100% production tested at temperature extremes for military devices.
TIMING DIAGRAM
AIN
CLK
DCO–
DCO+
FCO–
FCO+
D–
D+
N–1
tA
tEH
tCPD
N
tEL
tFCO
tPD
tFRAME
tDATA
MSB D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 MSB D10
(N – 10) (N – 10) (N – 10) (N – 10) (N – 10) (N – 10) (N – 10) (N – 10) (N – 10) (N – 10) (N – 10) (N – 10) (N – 9) (N – 9)
Figure 2. Timing Diagram
Rev. 0 | Page 5 of 16
5 Page 
90
85
80
75
70
65
60
55
–16 –15 –14 –13 –12 –11 –10 –9 –8 –7 –6 –5 –4 –3 –2 –1 0
BACK-OFF (dBFS)
Figure 10. SFDR vs. Backoff @ AIN with fIN = 70 MHz
90
85
80
75
70
65
60
55
–16 –15 –14 –13 –12 –11 –10 –9 –8 –7 –6 –5 –4 –3 –2 –1 0
BACK-OFF (dBFS)
Figure 11. SFDR vs. Backoff @ AIN with fIN = 110 MHz
90
85
80
75
70
65
60
55
–16 –15 –14 –13 –12 –11 –10 –9 –8 –7 –6 –5 –4 –3 –2 –1 0
BACK-OFF (dBFS)
Figure 12. SFDR vs. Backoff @ AIN with fIN = 140 MHz
AD15452
86
SFDR = 70MHz
84
82 SFDR = 110MHz
80
78
76 SFDR = 140MHz
74
72
70
68
66 SNR = 70MHz/110MHz/140MHz
64
62
–40
25 85
TEMPERATURE (°C)
Figure 13. SNR/SFDR vs. Temperature with FIN @ −9 dBFS
0.5
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
0
512 1024 1536 2048 2560 3072 3584 4096
CODE
Figure 14. Typical INL
Rev. 0 | Page 11 of 16
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet AD15452.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| AD15452 | 12-Bit 65 MSPS Quad A/D Converter | Analog Devices |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |