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ADUC7022 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer ADUC7022
Beschreibung Precision Analog Microcontroller
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 30 Seiten
ADUC7022 Datasheet, Funktion
Data Sheet
Precision Analog Microcontroller, 12-Bit
Analog I/O, ARM7TDMI MCU
ADuC7019/20/21/22/24/25/26/27/28/29
FEATURES
Analog I/O
Multichannel, 12-bit, 1 MSPS ADC
Up to 16 ADC channels1
Fully differential and single-ended modes
0 V to VREF analog input range
12-bit voltage output DACs
Up to 4 DAC outputs available1
On-chip voltage reference
On-chip temperature sensor (±3°C)
Voltage comparator
Microcontroller
ARM7TDMI core, 16-bit/32-bit RISC architecture
JTAG port supports code download and debug
Clocking options
Trimmed on-chip oscillator (±3%)
External watch crystal
External clock source up to 44 MHz
41.78 MHz PLL with programmable divider
Memory
62 kB Flash/EE memory, 8 kB SRAM
In-circuit download, JTAG-based debug
Software-triggered in-circuit reprogrammability
On-chip peripherals
UART, 2× I2C® and SPI serial I/O
Up to 40-pin GPIO port1
4× general-purpose timers
Wake-up and watchdog timers (WDT)
Power supply monitor
3-phase, 16-bit PWM generator1
Programmable logic array (PLA)
External memory interface, up to 512 kB1
Power
Specified for 3 V operation
Active mode: 11 mA @ 5 MHz, 40 mA @ 41.78 MHz
Packages and temperature range
From 40-lead 6 mm × 6 mm LFCSP to 80-lead LQFP1
Fully specified for –40°C to +125°C operation
Tools
Low cost QuickStart™ development system
Full third-party support
APPLICATIONS
Industrial control and automation systems
Smart sensors, precision instrumentation
Base station systems, optical networking
FUNCTIONAL BLOCK DIAGRAM
ADC0 TO ADC4,
ADC12 TO ADC14
ADC15
CMP0
CMP1
CMPOUT
VREF
XCLKI
XCLKO
RST
MUX
1MSPS
12-BIT ADC
TEMP
SENSOR
BAND GAP
REF
ADuC7019
12-BIT
DAC
12-BIT
DAC
12-BIT
DAC
OSC
AND PLL
PSM
POR
PLA
ARM7TDMI-BASED MCU WITH
ADDITIONAL PERIPHERALS
2k × 32 SRAM
31k × 16 FLASH/EEPROM
GPIO
4 GENERAL-
SERIAL I/O
PURPOSE TIMERS UART, SPI, I2C
JTAG
3-PHASE
PWM
(SEE NOTE 1)
DAC0
DAC1
DAC2
NOTES
1. SEE APPLICATION NOTE AN-798.
1 Depending on part model. See Ordering Guide for more information.
Figure 1.
Rev. G
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2005–2015 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com






ADUC7022 Datasheet, Funktion
ADuC7019/20/21/22/24/25/26/27/28/29
Data Sheet
ADC0 TO ADC9,
ADC12, ADC13
CMP0
CMP1
CMPOUT
VREF
XCLKI
XCLKO
RST
MUX
1MSPS
12-BIT ADC
TEMP
SENSOR
BAND GAP
REF
ADuC7024
12-BIT
DAC
12-BIT
DAC
OSC
AND PLL
PSM
POR
PLA
ARM7TDMI-BASED MCU WITH
ADDITIONAL PERIPHERALS
2k × 32 SRAM
31k × 16 FLASH/EEPROM
GPIO
4 GENERAL-
SERIAL I/O
PURPOSE TIMERS UART, SPI, I2C
JTAG
3-PHASE
PWM
(SEE NOTE 1)
DAC0
DAC1
PWM0H
PWM0L
PWM1H
PWM1L
PWM2H
PWM2L
NOTES
1. SEE APPLICATION NOTE AN-798.
Figure 5.
ADC0 TO ADC9,
ADC12, ADC13
CMP0
CMP1
CMPOUT
VREF
XCLKI
XCLKO
RST
MUX
1MSPS
12-BIT ADC
TEMP
SENSOR
BAND GAP
REF
ADuC7025
OSC
AND PLL
PSM
POR
PLA
ARM7TDMI-BASED MCU WITH
ADDITIONAL PERIPHERALS
2k × 32 SRAM
31k × 16 FLASH/EEPROM
GPIO
4 GENERAL-
SERIAL I/O
PURPOSE TIMERS UART, SPI, I2C
JTAG
NOTES
1. SEE APPLICATION NOTE AN-798.
Figure 6.
3-PHASE
PWM
(SEE NOTE 1)
PWM0H
PWM0L
PWM1H
PWM1L
PWM2H
PWM2L
Rev. G | Page 6 of 101

6 Page









ADUC7022 pdf, datenblatt
ADuC7019/20/21/22/24/25/26/27/28/29
Data Sheet
Parameter
MCU CLOCK RATE
From 32 kHz Internal Oscillator
From 32 kHz External Crystal
Using an External Clock
START-UP TIME
At Power-On
From Pause/Nap Mode
Min
0.05
0.05
From Sleep Mode
From Stop Mode
PROGRAMMABLE LOGIC ARRAY (PLA)
Pin Propagation Delay
Element Propagation Delay
POWER REQUIREMENTS13, 14
Power Supply Voltage Range
AVDD to AGND and IOVDD to IOGND
Analog Power Supply Currents
AVDD Current
2.7
DACVDD Current15
Digital Power Supply Current
IOVDD Current in Normal Mode
IOVDD Current in Pause Mode
IOVDD Current in Sleep Mode
Additional Power Supply Currents
ADC
DAC
ESD TESTS
HBM Passed Up To
FCIDM Passed Up To
Typ
326
41.78
130
24
3.06
1.58
1.7
12
2.5
200
400
3
7
11
40
25
250
600
2
0.7
700
Max
44
41.78
3.6
25
10
15
45
30
400
1000
4
0.5
Unit Test Conditions/Comments
kHz
MHz
MHz
MHz
ms
ns
μs
ms
ms
CD12 = 7
CD12 = 0
TA = 85°C
TA = 125°C
Core clock = 41.78 MHz
CD12 = 0
CD12 = 7
ns From input pin to output pin
ns
V
μA ADC in idle mode; all parts except ADuC7019
μA ADC in idle mode; ADuC7019 only
μA
Code executing from Flash/EE
mA CD12 = 7
mA CD12 = 3
mA CD12 = 0 (41.78 MHz clock)
mA CD12 = 0 (41.78 MHz clock)
μA TA = 85°C
μA TA = 125°C
mA @ 1 MSPS
mA @ 62.5 kSPS
μA per DAC
2.5 V reference, TA = 25°C
kV
kV
1 All ADC channel specifications are guaranteed during normal MicroConverter core operation.
2 Apply to all ADC input channels.
3 Measured using the factory-set default values in the ADC offset register (ADCOF) and gain coefficient register (ADCGN).
4 Not production tested but supported by design and/or characterization data on production release.
5 Measured using the factory-set default values in ADCOF and ADCGN with an external AD845 op amp as an input buffer stage as shown in Figure 59. Based on external ADC
system components; the user may need to execute a system calibration to remove external endpoint errors and achieve these specifications (see the Calibration section).
6 The input signal can be centered on any dc common-mode voltage (VCM) as long as this value is within the ADC voltage input range specified.
7 DAC linearity is calculated using a reduced code range of 100 to 3995.
8 DAC gain error is calculated using a reduced code range of 100 to internal 2.5 V VREF.
9 Endurance is qualified as per JEDEC Standard 22, Method A117 and measured at −40°C, +25°C, +85°C, and +125°C.
10 Retention lifetime equivalent at junction temperature (TJ) = 85°C as per JEDEC Standard 22m, Method A117. Retention lifetime derates with junction temperature.
11 Test carried out with a maximum of eight I/Os set to a low output level.
12 See the POWCON register.
13 Power supply current consumption is measured in normal, pause, and sleep modes under the following conditions: normal mode with 3.6 V supply, pause mode with
3.6 V supply, and sleep mode with 3.6 V supply.
14 IOVDD power supply current decreases typically by 2 mA during a Flash/EE erase cycle.
15 On the ADuC7019/20/21/22, this current must be added to the AVDD current.
Rev. G | Page 12 of 101

12 Page





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