DS3183 Datasheet PDF - Maxim Integrated Products
| Part Number | DS3183 | |
| Description | (DS3181 - DS3184) Single/Dual/Triple/Quad ATM/Packet PHYs | |
| Manufacturers | Maxim Integrated Products | |
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DS3181/DS3182/DS3183/DS3184
Single/Dual/Triple/Quad
ATM/Packet PHYs with Built-In LIU
GENERAL DESCRIPTION
The DS3181, DS3182, DS3183, and DS3184
(DS318x) integrate ATM cell/HDLC packet
processor(s) with a DS3/E3 framer(s) and LIU(s) to
map/demap ATM cells or packets into as many as
four DS3/E3 physical copper lines with DS3-framed,
E3-framed, or clear-channel data streams on per-port
basis.
APPLICATIONS
Access Concentrators Multiservice Access
SONET/SDH ADM
Platform (MSAP)
SONET/SDH Muxes
PBXs
Multiservice Protocol
Platform (MSPP)
Digital Cross Connect ATM and Frame Relay
Test Equipment
Equipment
Routers and Switches PDH Multiplexer/
Integrated Access
Demultiplexer
Device (IAD)
ORDERING INFORMATION
PART
DS3181*
DS3181N*
DS3182*
DS3182N*
DS3183*
DS3183N*
DS3184
DS3184N
TEMP RANGE
0°C to +70°C
-40°C to +85°C
0°C to +70°C
-40°C to +85°C
0°C to +70°C
-40°C to +85°C
0°C to +70°C
-40°C to +85°C
PIN-PACKAGE
400 TE-CSBGA (27mm x
27mm, 1.27mm pitch)
400 TE-CSBGA (27mm x
27mm, 1.27mm pitch)
400 TE-CSBGA (27mm x
27mm, 1.27mm pitch)
400 TE-CSBGA (27mm x
27mm, 1.27mm pitch)
400 TE-CSBGA (27mm x
27mm, 1.27mm pitch)
400 TE-CSBGA (27mm x
27mm, 1.27mm pitch)
400 TE-CSBGA (27mm x
27mm, 1.27mm pitch)
400 TE-CSBGA (27mm x
27mm, 1.27mm pitch)
*Future product—contact factory for availability.
POS-PHY and POS-PHY Level 3 are trademarks of PMC-Sierra, Inc.
FUNCTIONAL DIAGRAM
DS3/E3/STS-1
PORTS
DS3/E3
CELL/
FRAMER/
PACKET
FORMATTER PROCESSOR
DS318x
POS-PHY
OR
UTOPIA
FEATURES
§ Single (DS3181), Dual (DS3182), Triple
(DS3183), or Quad (DS3184) with Integrated LIU
ATM/Packet PHYs for DS3, E3, and Clear-
Channel 52Mbps (CC52)
§ Pin Compatible for Ease of Port Density
Migration in the Same PC Board Platform
§ Each Port Independently Configurable
§ Perform Receive Clock/Data Recovery and
Transmit Waveshaping
§ Jitter Attenuator can be Placed Either in the
Receive or Transmit Paths
§ Interfaces to 75W Coaxial Cable at Lengths Up to
380 Meters or 1246 Feet (DS3) or 440 Meters or
1443 Feet (E3)
§ Uses 1:2 Transformers on Both Tx and Rx
§ Universal PHYs Map ATM Cells and/or HDLC
Packets into DS3 or E3 Data Streams
§ UTOPIA L2/L3 or POS-PHY™ L2/L3 or SPI-3
Interface with 8-, 16-, or 32-Bit Bus Width
§ 66MHz UTOPIA L3 and POS-PHY L3 Clock
§ 52MHz UTOPIA L2 and POS-PHY L2 Clock
§ Ports Independently Configurable for Cell or
Packet Traffic in POS-PHY Bus Modes
§ Direct, PLCP, DSS, and Clear-Channel Cell
Mapping
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata.
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REV: 061604
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DS3181/DS3182/DS3183/DS3184
10.7.6 Packet Processor ............................................................................................................................... 148
10.7.7 FIFO ................................................................................................................................................... 150
10.7.8 System Loopback............................................................................................................................... 151
10.8 DS3/E3 PLCP FRAMER.............................................................................................................................. 153
10.8.1 General Description ........................................................................................................................... 153
10.8.2 Features ............................................................................................................................................. 153
10.8.3 Transmit PLCP Frame Processor ...................................................................................................... 154
10.8.4 Receive PLCP Frame Processor ....................................................................................................... 154
10.8.5 Transmit DS3 PLCP Frame Processor .............................................................................................. 154
10.8.6 Receive DS3 PLCP Frame Processor ............................................................................................... 157
10.8.7 Transmit E3 PLCP Frame Processor................................................................................................. 158
10.8.8 Receive E3 PLCP Frame Processor.................................................................................................. 161
10.9 FRACTIONAL PAYLOAD CONTROLLER ........................................................................................................... 163
10.9.1 General Description ........................................................................................................................... 163
10.9.2 Features ............................................................................................................................................. 163
10.9.3 Transmit Fractional Interface ............................................................................................................. 164
10.9.4 Transmit Fractional Controller............................................................................................................ 164
10.9.5 Receive Fractional Interface .............................................................................................................. 164
10.9.6 Receive Fractional Controller............................................................................................................. 164
10.10 DS3/E3 FRAMER / FORMATTER ................................................................................................................... 166
10.10.1 General Description ........................................................................................................................... 166
10.10.2 Features ............................................................................................................................................. 166
10.10.3 Transmit Formatter............................................................................................................................. 167
10.10.4 Receive Framer.................................................................................................................................. 167
10.10.5 C-bit DS3 Framer/Formatter .............................................................................................................. 171
10.10.6 M23 DS3 Framer/Formatter ............................................................................................................... 174
10.10.7 G.751 E3 Framer/Formatter............................................................................................................... 177
10.10.8 G.832 E3 Framer/Formatter............................................................................................................... 179
10.10.9 Clear-Channel Frame Processor ....................................................................................................... 184
10.11 HDLC OVERHEAD CONTROLLER.................................................................................................................. 184
10.11.1 General Description ........................................................................................................................... 184
10.11.2 Features ............................................................................................................................................. 185
10.11.3 Transmit FIFO .................................................................................................................................... 185
10.11.4 Transmit HDLC Overhead Processor ................................................................................................ 186
10.11.5 Receive HDLC Overhead Processor ................................................................................................. 186
10.11.6 Receive FIFO ..................................................................................................................................... 187
10.12 TRAIL TRACE CONTROLLER.......................................................................................................................... 187
10.12.1 General Description ........................................................................................................................... 187
10.12.2 Features ............................................................................................................................................. 188
10.12.3 Functional Description........................................................................................................................ 189
10.12.4 Transmit Data Storage ....................................................................................................................... 189
10.12.5 Transmit Trace ID Processor ............................................................................................................. 189
10.12.6 Transmit Trail Trace Processing ........................................................................................................ 189
10.12.7 Receive Trace ID Processor .............................................................................................................. 189
10.12.8 Receive Trail Trace Processing ......................................................................................................... 189
10.12.9 Receive Data Storage ........................................................................................................................ 190
10.13 FEAC CONTROLLER ................................................................................................................................... 191
10.13.1 General Description ........................................................................................................................... 191
10.13.2 Features ............................................................................................................................................. 191
10.13.3 Functional Description........................................................................................................................ 191
10.14 LINE ENCODER/DECODER............................................................................................................................ 193
10.14.1 General Description ........................................................................................................................... 193
10.14.2 Features ............................................................................................................................................. 193
10.14.3 B3ZS/HDB3 Encoder ......................................................................................................................... 193
10.14.4 Transmit Line Interface ...................................................................................................................... 194
10.14.5 Receive Line Interface ....................................................................................................................... 194
10.14.6 B3ZS/HDB3 Decoder ......................................................................................................................... 194
10.15 BERT......................................................................................................................................................... 196
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| Information | Total 30 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ DS3183.PDF Datasheet ] | |
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