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ADT7476A Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer ADT7476A
Beschreibung dBCool Remote Thermal Controller and Voltage Monitor
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 30 Seiten
ADT7476A Datasheet, Funktion
www.DataSheet4U.com
dBCoolRemote Thermal
Controller and Voltage Monitor
ADT7476A
FEATURES
Monitors up to five voltages
Improved TACH and PWM performance
Controls and monitors up to four fans
High and low frequency fan drive signal
One on-chip and two remote temperature sensors
Extended temperature measurement range up to 191°C
Automatic fan speed control mode controls system
cooling based on measured temperature
Enhanced acoustic mode dramatically reduces user
perception of changing fan speeds
Thermal protection feature via THERM output
Monitors performance impact of Intel® Pentium® 4 processor
Thermal control circuit via THERM input
3-wire and 4-wire fan speed measurement
Limit comparison of all monitored values
5 V support on all TACH and PWM channels
Meets SMBus 2.0 electrical specifications
GENERAL DESCRIPTION
The ADT7476A dBCOOL controller is a thermal monitor
and multiple PWM fan controller for noise-sensitive or power-
sensitive applications requiring active system cooling. The
ADT7476A can drive a fan using either a low or high frequency
drive signal and can monitor the temperature of up to two
remote sensor diodes plus its own internal temperature. The
part also measures and controls the speed of up to four fans, so
the fans operate at the lowest possible speed for minimum
acoustic noise.
The automatic fan speed control loop optimizes fan speed
for a given temperature. The effectiveness of the system’s
thermal solution can be monitored using the THERM input.
The ADT7476A also provides critical thermal protection to
the system using the bidirectional THERM pin as an output
to prevent system or component overheating.
VID5/GPIO5
VID4/GPIO4
VID3/GPIO3
VID2/GPIO2
VID1/GPIO1
VID0/GPIO0
GPIO6
PWM1
PWM2
PWM3
TACH1
TACH2
TACH3
TACH4
THERM
VCC
D1+
D1–
D2+
D2–
+5VIN
+12VIN
+2.5VIN
VCCP
FUNCTIONAL BLOCK DIAGRAM
ADDR
ADDREN SELECT SCL SDA SMBALERT
PWM
REGISTERS
AND
CONTROLLERS
(HF AND LF)
VCC TO ADT7476A
BAND GAP
TEMP. SENSOR
VID/GPIO
REGISTER
AUTOMATIC
FAN SPEED
CONTROL
FAN
SPEED
COUNTER
PERFORMANCE
MONITORING
THERMAL
PROTECTION
INPUT
SIGNAL
CONDITIONING
AND
ANALOG
MULTIPLEXER
SMBus
ADDRESS
SELECTION
SERIAL BUS
INTERFACE
ADT7476A
ADDRESS
POINTER
REGISTER
PWM
CONFIGURATION
REGISTERS
INTERRUPT
MASKING
ACOUSTIC
ENHANCEMENT
CONTROL
10-BIT
ADC
BAND GAP
REFERENCE
INTERRUPT
STATUS
REGISTERS
LIMIT
COMPARATORS
VALUE AND
LIMIT
REGISTERS
GND
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.






ADT7476A Datasheet, Funktion
ADT7476A
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
SDA 1
24 PWM1/XTO
SCL 2
GND 3
VCC 4
VID0/GPIO0 5
VID1/GPIO1 6
VID2/GPIO2 7
23 VCCP
22 +2.5VIN/THERM
21 +12VIN/VID5
ADT7476A
TOP VIEW
(Not to Scale)
20 +5VIN
19 VID4/GPIO4
18 D1+
VID3/GPIO3 8
17 D1–
TACH3 9
16 D2+
PWM2/SMBALERT 10
15 D2–
TACH1 11
14 TACH4/THERM/SMBALERT/GPIO6/ADDR SELECT
TACH2 12
13 PWM3/ADDREN
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
1 SDA
Digital I/O (Open Drain). SMBus bidirectional serial data. Requires SMBus pull-up.
2 SCL
Digital Input (Open Drain). SMBus serial clock input. Requires SMBus pull-up.
3 GND
Ground Pin.
4 VCC
Power Supply. Powered by 3.3 V standby, if monitoring in low power states is required. VCC is also monitored
through this pin.
5 VID0/
Digital Input. Voltage supply readouts from CPU. This value is read into the VID/GPIO register (0x43).
GPIO0
General-Purpose Open Drain Digital I/O.
6 VID1/
Digital Input. Voltage supply readouts from CPU. This value is read into the VID/GPIO register (0x43).
GPIO1
General-Purpose Open Drain Digital I/O.
7 VID2/
Digital Input. Voltage supply readouts from CPU. This value is read into the VID/GPIO register (0x43).
GPIO2
General-Purpose Open Drain Digital I/O.
8 VID3/
Digital Input. Voltage supply readouts from CPU. This value is read into the VID/GPIO register (0x43).
GPIO3
General-Purpose Open Drain Digital I/O.
9 TACH3 Digital Input (Open Drain). Fan tachometer input to measure speed of Fan 3.
10 PWM2/
Digital Output (Open Drain). Requires 10 kΩ typical pull-up. Pulse width modulated output to control Fan 2
speed. Can be configured as a high or low frequency drive.
SMBALERT
Digital Output (Open Drain). This pin can be reconfigured as an SMBALERT interrupt output to signal out-of-
limit conditions.
11 TACH1
Digital Input (Open Drain). Fan tachometer input to measure speed of Fan 1.
12 TACH2
Digital Input (Open Drain). Fan tachometer input to measure speed of Fan 2.
13 PWM3
Digital I/O (Open Drain). Pulse width modulated output to control the speed of Fan 3 and Fan 4. Requires 10 kΩ
typical pull-up. Can be configured as a high or low frequency drive.
ADDREN
If pulled low on power-up, the ADT7476A enters address select mode, and the state of Pin 14 (ADDR SELECT)
determines the ADT7476A’s slave address.
14 TACH4/
Digital Input (Open Drain). Fan tachometer input to measure speed of Fan 4.
THERM/
Alternatively, the pin can be reconfigured as a bidirectional THERM pin. Times and monitors assertions on the
THERM input. For example, it can be connected to the PROCHOT output of Intel’s Pentium 4 processor or to the
output of a trip point temperature sensor. Can be used as an output to signal overtemperature conditions.
SMBALERT/
Digital Output (Open Drain). This pin can be reconfigured as an SMBALERT interrupt output to signal out-of-
limit conditions.
GPIO6/
General-Purpose Open Drain Digital I/O.
ADDR SELECT If in address select mode, the logic state of this pin defines the SMBus device address.
15 D2–
Cathode Connection to Second Thermal Diode.
16 D2+
Anode Connection to Second Thermal Diode.
17 D1–
Cathode Connection to First Thermal Diode.
18 D1+
Anode Connection to First Thermal Diode.
Rev. 0 | Page 6 of 72

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ADT7476A pdf, datenblatt
ADT7476A
ADT7476A
ADDR SELECT
VCC
10kΩ
14
PWM3/ADDREN 13 NC
DO NOT LEAVE ADDREN
UNCONNECTED! CAN
CAUSE UNPREDICTABLE
ADDRESSES.
CARE SHOULD BE TAKEN TO ENSURE THAT PIN 13
(PWM3/ADDREN) IS EITHER TIED HIGH OR LOW. LEAVING PIN 13
FLOATING COULD CAUSE THE ADT7476A TO POWER UP WITH AN
UNEXPECTED ADDRESS.
NOTE THAT IF THE ADT7476A IS PLACED INTO ADDR SELECT
MODE, PINS 13 AND 14 CANNOT BE USED AS THE ALTERNATIVE
FUNCTIONS (PWM3, TACH4/THERM) UNLESS THE CORRECT
CIRCUIT IS MUXED IN AT THE CORRECT TIME OR DESIGNED TO
HANDLE THESE DUAL FUNCTIONS.
Figure 17. Unpredictable SMBus Address if Pin 13 is Unconnected
The ability to make hardwired changes to the SMBus slave
address allows the user to avoid conflicts with other devices
sharing the same serial bus, for example, if more than one
ADT7476A is used in a system.
The serial bus protocol operates as follows:
1. The master initiates data transfer by establishing a start
condition, which is defined as a high-to-low transition on
the serial data line SDA while the serial clock line SCL
remains high. This indicates that an address/data stream
follows. All slave peripherals connected to the serial bus
respond to the start condition and shift in the next eight
bits, consisting of a 7-bit address (MSB first), plus a R/W
bit, which determine the direction of the data transfer, that
is, whether data is written to or read from the slave device.
The peripheral whose address corresponds to the transmit-
ted address responds by pulling the data line low during
the low period before the ninth clock pulse, known as the
acknowledge bit. All other devices on the bus now remain
idle while the selected device waits for data to be read from
or written to it. If the R/W bit is a 0, the master writes to
the slave device. If the R/W bit is a 1, the master reads from
the slave device.
2. Data is sent over the serial bus in sequences of nine clock
pulses, eight bits of data followed by an acknowledge bit
from the slave device. Transitions on the data line must
occur during the low period of the clock signal and
remain stable during the high period. A low-to-high
transition, when the clock is high, can be interpreted
as a stop signal. The number of data bytes transmitted
over the serial bus in a single read or write operation is
limited only by what the master and slave devices
can handle.
3. When all data bytes have been read or written, stop
conditions are established. In write mode, the master pulls
the data line high during the 10th clock pulse to assert a
stop condition. In read mode, the master device overrides
the acknowledge bit by pulling the data line high during the
low period before the ninth clock pulse. This is known as no
acknowledge. The master then takes the data line low during
the low period before the 10th clock pulse, and then high
during the 10th clock pulse to assert a stop condition.
Any number of bytes of data can be transferred over the serial
bus in one operation. However, it is not possible to mix read
and write in one operation because the type of operation is
determined at the beginning and cannot subsequently be
changed without starting a new operation. In the ADT7476A,
write operations contain either one or two bytes, and read
operations contain one byte.
To write data to one of the device data registers or read data
from it, the address pointer register must be set so the correct
data register is addressed. Then, data can be written into that
register or read from it. The first byte of a write operation
always contains an address stored in the address pointer
register. If data is to be written to the device, then the write
operation contains a second data byte that is written to the
register selected by the address pointer register.
This write operation is illustrated in Figure 18. The device
address is sent over the bus, and then R/W is set to 0. This is
followed by two data bytes. The first data byte is the address of
the internal data register to be written to, which is stored in the
address pointer register. The second data byte is the data to be
written to the internal data register.
When reading data from a register, there are two possibilities:
1. If the ADT7476A’s address pointer register value is
unknown, or not the desired value, then it must first be set
to the correct value before data can be read from the
desired data register. This is done by performing a write to
the ADT7476A as before, but only the data byte containing
the register address is sent, because no data is written to
the register (see Figure 19).
A read operation is then performed consisting of the serial
bus address; R/W bit set to 1, followed by the data byte
read from the data register (see Figure 20.)
2. If the address pointer register is already known to be at the
desired address, data can be read from the corresponding
data register without first writing to the address pointer
register (see Figure 20).
Rev. 0 | Page 12 of 72

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