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ADSP-BF539F Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer ADSP-BF539F
Beschreibung Blackfin Embedded Processor
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 30 Seiten
ADSP-BF539F Datasheet, Funktion
www.DataSheet4U.com
a
Preliminary Technical Data
FEATURES
1.0 V to 1.2 V core VDD with on-chip voltage regulation
3.3 V tolerant I/O with specific 5 V tolerant pins
316-ball Pb-free mini-BGA package
Up to 500 MHz high performance Blackfin processor
Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs,
40-bit shifter
RISC-like register and instruction model for ease of
programming and compiler friendly support
Advanced debug, trace, and performance monitoring
MEMORY
148K bytes of on-chip memory:
16K bytes of instruction SRAM/cache
64K bytes of instruction SRAM
32K bytes of data SRAM
32K bytes of data SRAM/cache
4K bytes of scratchpad SRAM
512K x 16-bits or 256K x 16-bits of flash memory
(ADSP-BF539F only)
Four dual-channel memory DMA controllers
Memory management unit providing memory protection
Blackfin®
Embedded Processor
ADSP-BF539/ADSP-BF539F
External memory controller with glueless support
for SDRAM, SRAM, flash, and ROM
Flexible memory booting options from SPI®, external
memory
PERIPHERALS
Parallel peripheral interface (PPI),
supporting ITU-R 656 video data formats
Four dual-channel, full-duplex synchronous serial ports, sup-
porting 16 stereo I2S® channels
Two DMA controllers supporting 26 channels
Controller area network (CAN) 2.0B controller
Media transceiver (MXVR) for connection
to a MOST® network
Three SPI-compatible ports
Three timer/counters with PWM support
Three UARTs with support for IrDA®
Two TWI controllers compatible with I2C® industry standard
38 general purpose I/O pins (GPIO)
16 general purpose flag pins (GPF)
Real time clock
Watchdog timer
Debug/JTAG interface
On-chip PLL capable of 0.5x To 64x frequency multiplication
GPIO
PORT
C
GPIO
PORT
D
GPIO
PORT
E
TWI0-1
CAN 2.0B
MXVR
SPI1-2
UART1-2
SPORT2-3
VOLTAGE REGULATOR
JTAG TEST AND EMULATION
PERIPHERAL ACCESS BUS
B
INTERRUPT
CONTROLLER
DMA CORE
BUS 3
DMA
CONTROLLER1
L1
INSTRUCTION
MEMORY
L1
DATA
MEMORY
DMA
CONTROLLER0
DMA CORE
BUS 1
DMA
EXTERNAL
BUS 1
DMA CORE BUS 0
DMA
EXTERNAL
BUS 0
EXTERNAL PORT
FLASH, SDRAM CONTROL
WATCHDOG
TIMER
RTC
PPI
TIM ER 0- 2
SPI0
UART0
SPORT0-1
GPIO
PORT
F
512 KB OR 1 MB
FLASH MEMORY
(ADSP-BF539F ONLY)
BOOT ROM
Figure 1. Functional Block Diagram
Blackfin and the Blackfin logo are registered trademarks of Analog Devices, Inc.
Rev. PrF
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 © 2006 Analog Devices, Inc. All rights reserved.






ADSP-BF539F Datasheet, Funktion
ADSP-BF539/ADSP-BF539F
Preliminary Technical Data
ADDRESS ARITHMETIC UNIT
DA1 32
DA0 32
I3 L3 B3
I2 L2 B2
I1 L1 B1
I0 L0 B0
M3
M2
M1
M0
32
RAB
DAG1
DAG0
SP
FP
P5
P4
P3
P2
P1
P0
32
PREG
SD 32
LD1 32
LD0 32
32
32
R7.H
R6.H
R5.H
R4.H
R3.H
R2.H
R1.H
R0.H
R7.L
R6.L
R5.L
R4.L
R3.L
R2.L
R1.H
R0.L
16
88
BARREL
SHIFTER
40
ASTAT
16
8
8
40
SEQUENCER
ALIGN
DECODE
LOOP BUFFER
A0 40 40
32 32
DATA ARITHMETIC UNIT
Figure 2. Blackfin Processor Core
A1
CONTROL
UNIT
The second on-chip memory block is the L1 data memory, con-
sisting of two banks of up to 32K bytes each. Each memory bank
is configurable, offering both cache and SRAM functionality.
This memory block is accessed at full processor speed.
The third memory block is a 4K byte scratchpad SRAM which
runs at the same speed as the L1 memories, but is only accessible
as data SRAM and cannot be configured as cache memory.
External (Off-Chip) Memory
External memory is accessed via the EBIU. This 16-bit interface
provides a glueless connection to a bank of synchronous DRAM
(SDRAM) as well as up to four banks of asynchronous memory
devices including flash, EPROM, ROM, SRAM, and memory
mapped I/O devices.
The PC133-compliant SDRAM controller can be programmed
to interface to up to 128M bytes of SDRAM. The SDRAM con-
troller allows one row to be open for each internal SDRAM
bank, for up to four internal SDRAM banks, improving overall
system performance.
The asynchronous memory controller can be programmed to
control up to four banks of devices with very flexible timing
parameters for a wide variety of devices. Each bank occupies a
1M byte segment regardless of the size of the devices used, so
that these banks will only be contiguous if each is fully popu-
lated with 1M byte of memory.
Flash Memory (ADSP-BF539F only)
The ADSP-BF539F4 and ADSP-BF539F8 processors contain a
separate flash die, connected to the EBIU bus, within the pack-
age of the ADSP-BF539F processors. Figure 4 on Page 7 shows
how the flash memory die and Blackfin processor die are
connected.
The ADSP-BF539F4 contains a 4 Mbit (256K x 16-bits) bottom
boot sector flash memory. The ADSP-BF539F8 contains an 8
Mbit (512K x 16-bits) bottom boot sector flash memory. Fea-
tures include the following.
• access times as fast as 70 ns (EBIU registers be set
appropriately)
• sector protection
• one million write cycles per sector
• 20 year data retention
The Blackfin processor connects to the flash memory die with
address, data, chip enable, write enable, and output enable con-
trols as if it were an external memory device.
Rev. PrF | Page 6 of 68 | September 2006

6 Page









ADSP-BF539F pdf, datenblatt
ADSP-BF539/ADSP-BF539F
include support for 5 to 8 data bits, 1 or 2 stop bits, and none,
even, or odd parity. The UART ports support two modes of
operation:
• PIO (Programmed I/O) – The processor sends or receives
data by writing or reading I/O mapped UART registers.
The data is double buffered on both transmit and receive.
• DMA (Direct Memory Access) – The DMA controller
transfers both transmit and receive data. This reduces the
number and frequency of interrupts required to transfer
data to and from memory. The UARTs have two dedicated
DMA channels, one for transmit and one for receive. These
DMA channels have lower default priority than most DMA
channels because of their relatively low service rates.
The UART ports’ baud rate, serial data format, error code gen-
eration and status, and interrupts are programmable:
• Supporting bit rates ranging from (fSCLK/ 1,048,576) to
(fSCLK/16) bits per second.
• Supporting data formats from 7 to12 bits per frame.
• Both transmit and receive operations can be configured to
generate maskable interrupts to the processor.
The UART ports’ clock rate is calculated as:
UART Clock Rate
=
-------------------f--S--C--L---K-------------------
16 × UART_Divisor
Where the 16-bit UART_Divisor comes from the DLH register
(most significant 8 bits) and DLL register (least significant
8 bits).
In conjunction with the general purpose timer functions, auto-
baud detection is supported on UART0.
The capabilities of the UARTs are further extended with sup-
port for the Infrared Data Association (IrDA®) Serial Infrared
Physical Layer Link Specification (SIR) protocol.
PROGRAMMABLE I/O PINS
The ADSP-BF539/ADSP-BF539F processor has numerous
peripherals that may not all be required for every application.
Many of the pins thus have a secondary function, as general
purpose I/O pins. There are two types of programmable I/O
pins on the ADSP-BF539/ADSP-BF539F processor, with
slightly different functionality: programmable flags and general
purpose I/O.
Programmable Flags (PFx)
The ADSP-BF539/ADSP-BF539F processor has 16 bi-direc-
tional, general purpose Programmable Flag (PF15–0) pins.
Each programmable flag can be individually controlled by
manipulation of the flag control, status and interrupt registers:
• Flag Direction Control Register – Specifies the direction of
each individual PFx pin as input or output.
• Flag Control and Status Registers – The ADSP-
BF539/ADSP-BF539F processor employs a “write one to
modify” mechanism that allows any combination of indi-
vidual flags to be modified in a single instruction, without
affecting the level of any other flags. Four control registers
Preliminary Technical Data
are provided. One register is written in order to set flag val-
ues, one register is written in order to clear flag values, one
register is written in order to toggle flag values, and one
register is written in order to specify a flag value. Reading
the flag status register allows software to interrogate the
sense of the flags.
• Flag Interrupt Mask Registers – The two Flag Interrupt
Mask Registers allow each individual PFx pin to function as
an interrupt to the processor. Similar to the two Flag Con-
trol Registers that are used to set and clear individual flag
values, one Flag Interrupt Mask Register sets bits to enable
interrupt function, and the other Flag Interrupt Mask reg-
ister clears bits to disable interrupt function. PFx pins
defined as inputs can be configured to generate hardware
interrupts, while output PFx pins can be triggered by soft-
ware interrupts.
• Flag Interrupt Sensitivity Registers – The two Flag Inter-
rupt Sensitivity Registers specify whether individual PFx
pins are level- or edge-sensitive and specify—if edge-sensi-
tive—whether just the rising edge or both the rising and
falling edges of the signal are significant. One register
selects the type of sensitivity, and one register selects which
edges are significant for edge-sensitivity.
General Purpose I/O
The ADSP-BF539/ADSP-BF539F has 38 general-purpose I/O
pins that are multiplexed with other peripherals. They are
arranged into ports C, D, and E, as shown in Table 4 on Page 13.
The GPIO differ from the Programmable Flags in that the GPIO
pins cannot generate interrupts to the processor.
The general purpose I/O pins may be individually controlled by
manipulation of the control and status registers. These pins will
not cause interrupts to be generated to the processor, but may
be polled to determine their status.
• GPIO direction control register – Specifies the direction of
each individual GPIOx pin as input or output.
• GPIO control and status registers – The ADSP-
BF539/ADSP-BF539F processor employs a “write one to
modify” mechanism that allows any combination of indi-
vidual GPIO to be modified in a single instruction, without
affecting the level of any other GPIO. Four control registers
and a data register are provided for each GPIO port. One
register is written in order to set GPIO values, one register
is written in order to clear GPIO values, one register is
written in order to toggle GPIO values, and one register is
written in order to specify a GPIO input or output. Reading
the GPIO data allows software to determine the state of the
input GPIO pins.
Note that the GP pin is used to specify the status of the GPIO
pins PC9–PC4 at power up. If GP is tied high, then pins
PC9–PC4 are configured as GPIO after reset. The pins cannot
be reconfigured through software, and special care must be
taken with the MLF pin. If the GP pin is tied low, then the pins
are configured as MXVR pins after reset, but may be reconfig-
ured as GPIO pins through software.
Rev. PrF | Page 12 of 68 | September 2006

12 Page





SeitenGesamt 30 Seiten
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