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ADSP-BF536 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer ADSP-BF536
Beschreibung (ADSP-BF534 - ADSP-BF537) Blackfin Embedded Processor
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 30 Seiten
ADSP-BF536 Datasheet, Funktion
www.DataSheet4U.com
a
Blackfin®
Embedded Processor
ADSP-BF534/ADSP-BF536/ADSP-BF537
FEATURES
Up to 600 MHz high performance Blackfin processor
Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs,
40-bit shifter
RISC-like register and instruction model for ease of
programming and compiler-friendly support
Advanced debug, trace, and performance monitoring
0.8 V to 1.2 V core VDD with on-chip voltage regulation
2.5 V and 3.3 V-tolerant I/O with specific 5 V-tolerant pins
182-ball and 208-ball MBGA packages
MEMORY
Up to 132K bytes of on-chip memory comprised of:
Instruction SRAM/cache; instruction SRAM;
data SRAM/cache; additional dedicated data SRAM;
scratchpad SRAM (see Table 1 on Page 3 for available
memory configurations)
External memory controller with glueless support for SDRAM
and asynchronous 8-bit and 16-bit memories
Flexible booting options from external flash, SPI and TWI
memory or from SPI, TWI, and UART host devices
Memory management unit providing memory protection
PERIPHERALS
IEEE 802.3-compliant 10/100 Ethernet MAC (ADSP-BF536 and
ADSP-BF537 only)
Controller area network (CAN) 2.0B interface
Parallel peripheral interface (PPI), supporting ITU-R 656
video data formats
Two dual-channel, full-duplex synchronous serial ports
(SPORTs), supporting eight stereo I2S channels
12 peripheral DMAs, 2 mastered by the Ethernet MAC
Two memory-to-memory DMAs with external request lines
Event handler with 32 interrupt inputs
Serial peripheral interface (SPI)-compatible
Two UARTs with IrDA® support
Two-wire interface (TWI) controller
Eight 32-bit timer/counters with PWM support
Real-time clock (RTC) and watchdog timer
32-bit core timer
48 general-purpose I/Os (GPIOs), 8 with high current drivers
On-chip PLL capable of 1؋ to 63؋ frequency multiplication
Debug/JTAG interface
VOLTAGE REGULATOR
JTAG TEST AND EMULATION
PERIPHERAL ACCESS BUS
WATCHDOG TIMER
B
INTERRUPT
CONTROLLER
RTC
CAN
TWI
L1
INSTRUCTION
MEMORY
EXTERNAL
ACCESS
BUS
L1
DATA
MEMORY
DMA
CONTROLLER
DMA CORE BUS
EXTERNAL PORT
FLASH, SDRAM CONTROL
16
BOOT ROM
SPORT0
SPORT1
PPI
UART 0-1
SPI
TIMERS 0-7
ETHERNET MAC
(ADSP-BF536/
BF537 ONLY)
PORT
J
GPIO
PORT
G
GPIO
PORT
F
GPIO
PORT
H
Figure 1. Functional Block Diagram
Blackfin and the Blackfin logo are registered trademarks of Analog Devices, Inc.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2006 Analog Devices, Inc. All rights reserved.






ADSP-BF536 Datasheet, Funktion
ADSP-BF534/ADSP-BF536/ADSP-BF537
ADSP-BF534/ADSP-BF537 MEMORY MAP
0xFFFF FFFF
0xFFE0 0000
0xFFC0 0000
0xFFB0 1000
0xFFB0 0000
0xFFA1 4000
0xFFA1 0000
0xFFA0 C000
0xFFA0 8000
0xFFA0 0000
0xFF90 8000
0xFF90 4000
0xFF90 0000
0xFF80 8000
0xFF80 4000
0xFF80 0000
0xEF00 0800
0xEF00 0000
0x2040 0000
0x2030 0000
0x2020 0000
0x2010 0000
0x2000 0000
0x0000 0000
CORE MMR REGISTERS (2M BYTES)
SYSTEM MMR REGISTERS (2M BYTES)
RESERVED
SCRATCHPAD SRAM (4K BYTES)
RESERVED
INSTRUCTION SRAM/CACHE (16K BYTES)
RESERVED
INSTRUCTION BANK B SRAM (16K BYTES)
INSTRUCTION BANK A SRAM (32K BYTES)
RESERVED
DATA BANK B SRAM/CACHE (16K BYTES)
DATA BANK B SRAM (16K BYTES)
RESERVED
DATA BANK A SRAM/CACHE (16K BYTES)
DATA BANK A SRAM (16K BYTES)
RESERVED
BOOT ROM (2K BYTES)
RESERVED
ASYNC MEMORY BANK 3 (1M BYTES)
ASYNC MEMORY BANK 2 (1M BYTES)
ASYNC MEMORY BANK 1 (1M BYTES)
ASYNC MEMORY BANK 0 (1M BYTES)
SDRAM MEMORY (16M BYTES TO 512M BYTES)
0xFFFF FFFF
0xFFE0 0000
0xFFC0 0000
0xFFB0 1000
0xFFB0 0000
0xFFA1 4000
0xFFA1 0000
0xFFA0 C000
0xFFA0 8000
0xFFA0 0000
0xFF90 8000
0xFF90 4000
0xFF90 0000
0xFF80 8000
0xFF80 4000
0xFF80 0000
0xEF00 0800
0xEF00 0000
0x2040 0000
0x2030 0000
0x2020 0000
0x2010 0000
0x2000 0000
0x0000 0000
ADSP-BF536 MEMORY MAP
CORE MMR REGISTERS (2M BYTES)
SYSTEM MMR REGISTERS (2M BYTES)
RESERVED
SCRATCHPAD SRAM (4K BYTES)
RESERVED
INSTRUCTION SRAM/CACHE (16K BYTES)
RESERVED
INSTRUCTION BANK B SRAM (16K BYTES)
INSTRUCTION BANK A SRAM (32K BYTES)
RESERVED
DATA BANK B SRAM/CACHE (16K BYTES)
RESERVED
RESERVED
DATA BANK A SRAM/CACHE (16K BYTES)
RESERVED
RESERVED
BOOT ROM (2K BYTES)
RESERVED
ASYNC MEMORY BANK 3 (1M BYTES)
ASYNC MEMORY BANK 2 (1M BYTES)
ASYNC MEMORY BANK 1 (1M BYTES)
ASYNC MEMORY BANK 0 (1M BYTES)
SDRAM MEMORY (16M BYTES TO 512M BYTES)
Figure 3. ADSP-BF534/ADSP-BF536/ADSP-BF537 Memory Maps
Booting
The Blackfin processor contains a small on-chip boot kernel,
which configures the appropriate peripheral for booting. If the
Blackfin processor is configured to boot from boot ROM mem-
ory space, the processor starts executing from the on-chip boot
ROM. For more information, see Booting Modes on Page 16.
Event Handling
The event controller on the Blackfin processor handles all asyn-
chronous and synchronous events to the processor. The
Blackfin processor provides event handling that supports both
nesting and prioritization. Nesting allows multiple event service
routines to be active simultaneously. Prioritization ensures that
servicing of a higher priority event takes precedence over servic-
ing of a lower priority event. The controller provides support for
five different types of events:
• Emulation – An emulation event causes the processor to
enter emulation mode, allowing command and control of
the processor via the JTAG interface.
• Reset – This event resets the processor.
• Nonmaskable Interrupt (NMI) – The NMI event can be
generated by the software watchdog timer or by the NMI
input signal to the processor. The NMI event is frequently
used as a power-down indicator to initiate an orderly shut-
down of the system.
• Exceptions – Events that occur synchronously to program
flow (in other words, the exception is taken before the
instruction is allowed to complete). Conditions such as
data alignment violations and undefined instructions cause
exceptions.
• Interrupts – Events that occur asynchronously to program
flow. They are caused by input pins, timers, and other
peripherals, as well as by an explicit software instruction.
Each event type has an associated register to hold the return
address and an associated return-from-event instruction. When
an event is triggered, the state of the processor is saved on the
supervisor stack.
The Blackfin processor event controller consists of two stages,
the core event controller (CEC) and the system interrupt con-
troller (SIC). The core event controller works with the system
interrupt controller to prioritize and control all system events.
Rev. B | Page 6 of 68 | July 2006

6 Page









ADSP-BF536 pdf, datenblatt
ADSP-BF534/ADSP-BF536/ADSP-BF537
• Programmable Rx address filters, including a 64-bit
address hash table for multicast and/or unicast frames, and
programmable filter modes for broadcast, multicast, uni-
cast, control, and damaged frames.
• Advanced power management supporting unattended
transfer of Rx and Tx frames and status to/from external
memory via DMA during low-power sleep mode.
• System wakeup from sleep operating mode upon magic
packet or any of four user-definable wakeup frame filters.
• Support for 802.3Q tagged VLAN frames.
• Programmable MDC clock rate and preamble suppression.
• In RMII operation, 7 unused pins may be configured as
GPIO pins for other purposes.
PORTS
The ADSP-BF534/ADSP-BF536/ADSP-BF537 processors
group the many peripheral signals to four ports—Port F, Port G,
Port H, and Port J. Most of the associated pins are shared by
multiple signals. The ports function as multiplexer controls.
Eight of the pins (Port F7–0) offer high source/high sink current
capabilities.
General-Purpose I/O (GPIO)
The processors have 48 bidirectional, general-purpose I/O
(GPIO) pins allocated across three separate GPIO modules—
PORTFIO, PORTGIO, and PORTHIO, associated with Port F,
Port G, and Port H, respectively. Port J does not provide GPIO
functionality. Each GPIO-capable pin shares functionality with
other processor peripherals via a multiplexing scheme; however,
the GPIO functionality is the default state of the device upon
power-up. Neither GPIO output or input drivers are active by
default. Each general-purpose port pin can be individually con-
trolled by manipulation of the port control, status, and interrupt
registers:
• GPIO direction control register – Specifies the direction of
each individual GPIO pin as input or output.
• GPIO control and status registers – The processors employ
a “write one to modify” mechanism that allows any combi-
nation of individual GPIO pins to be modified in a single
instruction, without affecting the level of any other GPIO
pins. Four control registers are provided. One register is
written in order to set pin values, one register is written in
order to clear pin values, one register is written in order to
toggle pin values, and one register is written in order to
specify a pin value. Reading the GPIO status register allows
software to interrogate the sense of the pins.
• GPIO interrupt mask registers – The two GPIO interrupt
mask registers allow each individual GPIO pin to function
as an interrupt to the processor. Similar to the two GPIO
control registers that are used to set and clear individual
pin values, one GPIO interrupt mask register sets bits to
enable interrupt function, and the other GPIO interrupt
mask register clears bits to disable interrupt function.
GPIO pins defined as inputs can be configured to generate
hardware interrupts, while output pins can be triggered by
software interrupts.
• GPIO interrupt sensitivity registers – The two GPIO inter-
rupt sensitivity registers specify whether individual pins are
level- or edge-sensitive and specify—if edge-sensitive—
whether just the rising edge or both the rising and falling
edges of the signal are significant. One register selects the
type of sensitivity, and one register selects which edges are
significant for edge-sensitivity.
PARALLEL PERIPHERAL INTERFACE (PPI)
The ADSP-BF534/ADSP-BF536/ADSP-BF537 processors pro-
vide a parallel peripheral interface (PPI) that can connect
directly to parallel A/D and D/A converters, ITU-R-601/656
video encoders and decoders, and other general-purpose
peripherals. The PPI consists of a dedicated input clock pin, up
to 3 frame synchronization pins, and up to 16 data pins.
In ITU-R-656 modes, the PPI receives and parses a data stream
of 8-bit or 10-bit data elements. On-chip decode of embedded
preamble control and synchronization information
is supported.
Three distinct ITU-R-656 modes are supported:
• Active video only mode – The PPI does not read in any
data between the End of Active Video (EAV) and Start of
Active Video (SAV) preamble symbols, or any data present
during the vertical blanking intervals. In this mode, the
control byte sequences are not stored to memory; they are
filtered by the PPI.
• Vertical blanking only mode – The PPI only transfers verti-
cal blanking interval (VBI) data, as well as horizontal
blanking information and control byte sequences on
VBI lines.
• Entire field mode – The entire incoming bitstream is read
in through the PPI. This includes active video, control pre-
amble sequences, and ancillary data that may be embedded
in horizontal and vertical blanking intervals.
Though not explicitly supported, ITU-R-656 output functional-
ity can be achieved by setting up the entire frame structure
(including active video, blanking, and control information) in
memory and streaming the data out the PPI in a frame sync-less
mode. The processor’s 2-D DMA features facilitate this transfer
by allowing the static frame buffer (blanking and control codes)
to be placed in memory once, and simply updating the active
video information on a per-frame basis.
The general-purpose modes of the PPI are intended to suit a
wide variety of data capture and transmission applications. The
modes are divided into four main categories, each allowing up
to 16 bits of data transfer per PPI_CLK cycle:
• Data receive with internally generated frame syncs
• Data receive with externally generated frame syncs
• Data transmit with internally generated frame syncs
• Data transmit with externally generated frame syncs
Rev. B | Page 12 of 68 | July 2006

12 Page





SeitenGesamt 30 Seiten
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