ADSP-21371 Datasheet PDF - Analog Devices
| Part Number | ADSP-21371 | |
| Description | SHARC Processor | |
| Manufacturers | Analog Devices | |
| Logo |  |
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SHARC Processor
ADSP-21371/ADSP-21375
SUMMARY
High performance 32-bit/40-bit floating point processor
optimized for high performance audio processing
Single-instruction, multiple-data (SIMD) computational
architecture
On-chip memory, ADSP-21371—1M bits of on-chip SRAM
and 4M bits of on-chip mask-programmable ROM
On-chip memory, ADSP-21375—0.5M bits of on-chip
SRAM and 2M bits of on-chip mask-programmable ROM
Code compatible with all other members of the SHARC family
The ADSP-21371/ADSP-21375 processors are available with a
200/266 MHz core instruction rate with unique audiocen-
tric peripherals such as the digital applications interface,
S/PDIF transceiver, serial ports, precision clock generators,
and more. For complete ordering information, see Order-
ing Guide on Page 56.
DEDICATED AUDIO COMPONENTS
ADSP-21371—S/PDIF-compatible digital audio
receiver/transmitter
ADSP-21371—8 dual data line serial ports that operate at up
to 33 Mbps on each data line — each has a clock, frame
sync, and two data lines that can be configured as either a
receiver or transmitter pair
16 PWM outputs configured as four groups of four outputs
ROM-based security features include
JTAG access to memory permitted with a 64-bit key
Protected memory regions that can be assigned to limit
access under program control to sensitive code
PLL has a wide variety of software and hardware multi-
plier/divider ratios
Available in a 208-lead LQFP_EP package
SIMD Core
Instruction
Cache
5 stage
Sequencer
DAG1/2
Timer
PEx PEy
FLAGx/IRQx/
TMREXP
JTAG
Block 0
RAM/ROM
Internal Memory
Block 1
RAM/ROM
Block 2
RAM
Block 3
RAM
S
DMD 64-BIT
PMD 64-BIT
Core Bus
Cross Bar
DMD 64-BIT
PMD 64-BIT
PERIPHERAL BUS
32-BIT
EPD BUS 48-BIT
B0D
64-BIT
B1D
64-BIT
B2D
64-BIT
B3D
64-BIT
Internal Memory I/F
IODO 32-BIT
IOD1
32-BIT
PERIPHERAL BUS
IOD0 BUS
MTM/
D TCP
EP
CORE PCG TIMER
FLAGS C-D
1-0 TWI SPI/B UART
PCG S/PDIF IDP/ SPORT
A-D Tx/Rx PDAP 7-0
7-0
CORE PWM
FLAGS 3-0
AMI SDRAM
DPI Routing/Pins
DPI Peripherals
DAI Routing/Pins
DAI Peripherals
Figure 1. Functional Block Diagram
External Port Pin MUX
Peripherals
External
Port
SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.
Rev. D
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.
Tel: 781.329.4700
©2013 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
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Data Register File
Each processing element contains a general-purpose data regis-
ter file. The register files transfer data between the computation
units and the data buses, and store intermediate results. These
10-port, 32-register (16 primary, 16 secondary) register files,
combined with the SHARC’s enhanced Harvard architecture,
allow unconstrained data flow between computation units and
internal memory. The registers in PEX are referred to as
R0–R15 and in PEY as S0–S15.
Context Switch
Many of the processor’s registers have secondary registers that
can be activated during interrupt servicing for a fast context
switch. The data registers in the register file, the DAG registers,
and the multiplier result register all have secondary registers.
The primary registers are active at reset, while the secondary
registers are activated by control bits in a mode control register.
Universal Registers
Universal registers can be used for general purpose tasks. The
USTAT (4) registers allow easy bit manipulations (Set, Clear,
Toggle, Test, XOR) for all system registers (control/status) of
the core.
The data bus exchange register PX permits data to be passed
between the 64-bit PM data bus and the 64-bit DM data bus, or
between the 40-bit register file and the PM data bus. These reg-
isters contain hardware to handle the data width difference.
Timer
The processors contain a core timer that can generate periodic
software interrupts. The core timer can be configured to use
FLAG3 as a timer expired signal.
Single-Cycle Fetch of an Instruction and Four Operands
The processors feature an enhanced Harvard architecture in
which the data memory (DM) bus transfers data and the pro-
gram memory (PM) bus transfers both instructions and data
(see Figure 2). With the processor’s separate program and data
memory buses and on-chip instruction cache, the processor can
simultaneously fetch four operands (two over each data bus)
and one instruction (from the cache), all in a single cycle.
Instruction Cache
The processors include an on-chip instruction cache that
enables three-bus operation for fetching an instruction and four
data values. The cache is selective—only the instructions whose
fetches conflict with PM bus data accesses are cached. This
cache allows full speed execution of core, looped operations
such as digital filter multiply-accumulates, and FFT butterfly
processing.
Data Address Generators with Zero-Overhead Hardware
Circular Buffer Support
The processors’s two data address generators (DAGs) are used
for indirect addressing and implementing circular data buffers
in hardware. Circular buffers allow efficient programming of
delay lines and other data structures required in digital signal
ADSP-21371/ADSP-21375
processing, and are commonly used in digital filters and Fourier
transforms. The two DAGs contain sufficient registers to allow
the creation of up to 32 circular buffers (16 primary register sets,
16 secondary). The DAGs automatically handle address pointer
wraparound, reduce overhead, increase performance, and sim-
plify implementation. Circular buffers can start and end at any
memory location.
Flexible Instruction Set
The 48-bit instruction word accommodates a variety of parallel
operations, for concise programming. For example, the proces-
sors can conditionally execute a multiply, an add, and a subtract
in both processing elements while branching and fetching up to
four 32-bit values from memory—all in a single instruction.
On-Chip Memory
The ADSP-21371 processor contains 1 megabit of internal RAM
and four megabits of internal mask-programmable ROM (see
Table 3 on Page 6) and the ADSP-21375 processor contains 0.5
megabits of internal RAM and two megabits of internal mask-
programmable ROM (see Table 4 on Page 7). Each block can be
configured for different combinations of code and data storage.
Each memory block supports single-cycle, independent accesses
by the core processor and I/O processor. The processor’s mem-
ory architecture, in combination with its separate on-chip buses,
allow two data transfers from the core and one from the I/O
processor, in a single cycle.
The ADSP-21371 processor’s SRAM can be configured as a
maximum of 32k words of 32-bit data, 64k words of 16-bit data,
21.3k words of 48-bit instructions (or 40-bit data), or combina-
tions of different word sizes up to 1 megabit. All of the memory
can be accessed as 16-bit, 32-bit, 48-bit, or 64-bit words. A 16-
bit floating-point storage format is supported that effectively
doubles the amount of data that may be stored on-chip. Conver-
sion between the 32-bit floating-point and 16-bit floating-point
formats is performed in a single instruction. While each mem-
ory block can store combinations of code and data, accesses are
most efficient when one block stores data using the DM bus for
transfers, and the other block stores instructions and data using
the PM bus for transfers.
Using the DM bus and PM buses, with one bus dedicated to a
memory block, assures single-cycle execution with two data
transfers. In this case, the instruction must be available in
the cache.
On-Chip Memory Bandwidth
The internal memory architecture allows four accesses at the
same time to any of the four blocks, assuming no block con-
flicts. The total bandwidth is gained with DMD and PMD buses
(2 64-bits, core CLK) and the IOD0/1 buses (2 32-bit,
PCLK).
ROM-Based Security
The processors have a ROM security feature that provides hard-
ware support for securing user software code by preventing
unauthorized reading from the internal code when enabled.
When using this feature, the processor does not boot-load any
Rev. D | Page 5 of 56 | April 2013
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| Part Number | Description | MFRS |
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