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PDF ADC082500 Data sheet ( Hoja de datos )
| Número de pieza | ADC082500 | |
| Descripción | 2.5 GSPS A/D Converter | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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ADVANCE INFORMATION
August 2006
ADC082500
High Performance, Low Power, 8-Bit, 2.5 GSPS A/D
Converter
General Description
Note: This product is currently in development. - ALL
specifications are design targets and are subject to
change.
The ADC082500 is a single, low power, high performance
CMOS analog-to-digital converter that digitizes signals to 8
bits resolution at sampling rates up to 3.4 GSPS. Consuming
a typical 1.8 Watts at 2.5 GSPS from a single 1.9 Volt supply,
this device is guaranteed to have no missing codes over the
full operating temperature range. The unique folding and
interpolating architecture, the fully differential comparator
design, the innovative design of the internal sample-and-
hold amplifier and the self-calibration scheme enable a very
flat response of all dynamic parameters up to Nyquist, pro-
ducing a high 7.0 ENOB with a 748 MHz input Signal. A 2.5
GHz sample rate will provide a 10-18 B.E.R. The ADC082500
achieves a 2.5GSPS sampling rate by utilizing both the
rising and falling edge of a 1.25 GSPS input clock. Output
formatting is offset binary and the LVDS digital outputs are
compliant with IEEE 1596.3-1996, with the exception of an
adjustable common mode voltage between 0.8V and 1.2V.
The ADC has a 1:4 demultiplexer that feeds four LVDS
buses and reduces the output data rate on each bus to a
quarter of the sampling rate. The ADC can be programmed
into the 1:2 Output Mode where the data is output on the Dc
and Dd channels at the rate of the input clock.
The converter typically consumes less than 20 mW in the
Power Down Mode and is available in a 128-lead, thermally
enhanced exposed pad LQFP and operates over the Indus-
trial (-40˚C ≤ TA ≤ +85˚C) temperature range.
Features
n Internal Sample-and-Hold
n Single +1.9V ±0.1V Operation
n Choice of SDR or DDR output clocking
n 1:2 or 1:4 Selectable Output Demux
n Clock Phase Adjust for Multiple ADC Synchronization
n Guaranteed No Missing Codes
n Serial Interface for Extended Control
n Fine Adjustment of Input Full-Scale Range and Offset
n Duty Cycle Corrected Sample Clock
n Test pattern
Key Specifications
n Resolution
n Max Conversion Rate
n Bit Error Rate
n ENOB @ 748 MHz Input
n SNR @ 748 MHz
n Full Power Bandwidth
n Power Consumption
— Operating
— Power Down Mode
8 Bits
2.5 GSPS (min)
10-18 (typ)
7.0 Bits (typ)
44 dB (typ)
TBD GHz (typ)
1.8 W (typ)
20 mW (typ)
Applications
n Direct RF Down Conversion
n Digital Oscilloscopes
n Satellite Set-top boxes
n Communications Systems
n Test Instrumentation
© 2006 National Semiconductor Corporation DS201984
www.national.com
1 page  
Pin Descriptions and Equivalent Circuits (Continued)
Pin Functions
Pin No.
Symbol
Equivalent Circuit
Description
10 CLK+
11 CLK-
LVDS Clock input pins for the ADC. The differential clock
signal must be a.c. coupled to these pins. The input signal is
sampled on the falling edge of CLK+. See Section 1.1.2 for a
description of acquiring the input and Section 2.3 for an
overview of the clock inputs.
18 VIN+
19 VIN−
7 VCMO
31 VBG
126 CalRun
32 REXT
34 Tdiode_P
35 Tdiode_N
Analog signal inputs to the ADC. The differential full-scale
input range is 650 mVP-P when the FSR pin is low, or 870
mVP-P when the FSR pin is high.
Common Mode Voltage. The voltage output at this pin is
required to be the common mode input voltage at VIN+ and
VIN− when d.c. coupling is used. This pin should be grounded
when a.c. coupling is used at the analog inputs. This pin is
capable of sourcing or sinking 100µA. See Section 2.2.
Bandgap output voltage capable of 100 µA source/sink.
Calibration Running indication. This pin is at a logic high
when calibration is running.
External bias resistor connection. Nominal value is 3.3k-Ohms
(±0.1%) to ground. See Section 1.1.1.
Temperature Diode Positive (Anode) and Negative (Cathode)
for die temperature measurements. See Section 2.6.2.
5 www.national.com
5 Page 
Converter Electrical Characteristics (Continued)
NOTE: This product is currently in development and the parameters specified in this section are DESIGN TARGETS.
The specifications in this section cannot be guaranteed until device characterization has taken place. The following
specifications apply after calibration for VA = VDR = +1.9VDC, OutV = 1.9V, VIN FSR (a.c. coupled) = differential 870mVP-P, CL
= 10 pF, Differential, a.c. coupled Sinewave Input Clock, fCLK = 1.25GHz at 0.5VP-P with 50% duty cycle, VBG = Floating, Non-
Extended Control Mode, SDR Mode, REXT = 3300Ω ±0.1%, Analog Signal Source Impedance = 100Ω Differential. Boldface
limits apply for TA = TMIN to TMAX. All other limits TA = 25˚C, unless otherwise noted. (Notes 6, 7)
Symbol
Parameter
Conditions
Typical
(Note 8)
Limits
(Note 8)
Units
(Limits)
DIGITAL OUTPUT CHARACTERISTICS
∆ VOS
Output Offset Voltage Change
Between Logic Levels
±1 mV
Output+ & Output- connected to
IOS
Output Short Circuit Current
0.8V
±4
mA
ZO Differential Output Impedance
POWER SUPPLY CHARACTERISTICS
100 Ohms
PD = Low
IA Analog Supply Current PD = High
745
10.2
TBD
TBD
mA (max)
mA (max)
PD = Low
IDR
Output Driver Supply Current
PD = High
200
0.012
TBD
TBD
mA (max)
mA (max)
PD Power Consumption
PD = Low
PD = High
1.8
TBD
W (max)
20
TBD
mW (max)
PSRR1
PSRR2
D.C. Power Supply Rejection
Ratio
A.C. Power Supply Rejection
Ratio
Change in Full Scale Error with
change in VA from 1.8V to 2.0V
248 MHz, 50mVP-P riding on VA
30
51
dB
dB
AC ELECTRICAL CHARACTERISTICS
fCLK1
Maximum Input Clock
Frequency
Sampling rate is 2x clock input
1.7
1.25
GHz (min)
fCLK2
Minimum Input Clock
Frequency
Sampling rate is 2x clock input
500
MHz
Input Clock Duty Cycle
500MHz ≤ Input clock frequency ≤
1.25 GHz (Note 12)
50
20 % (min)
80 % (max)
tCL Input Clock Low Time
tCH Input Clock High Time
DCLK Duty Cycle
(Note 11)
(Note 11)
(Note 11)
333 133 ps (min)
333 133 ps (min)
45 % (min)
50
55 % (max)
tRS
tRH
tSD
tRPW
Reset Setup Time
Reset Hold Time
Syncronizing Edge to DCLK
Output Delay
Reset Pulse Width
(Note 11)
(Note 11)
fCLKIN = 1.25 GHz
fCLKIN = 500 MHz
(Note 11)
150
250
TBD
TBD
ps
ps
ns
Clock Cycles
4
(min)
Differential Low to High
tLHT Transition Time
10% to 90%, CL = 2.5 pF
250
ps
Differential High to Low
tHLT Transition Time
10% to 90%, CL = 2.5 pF
250
ps
50% of DCLK transition to 50% of
tOSK
DCLK to Data Output Skew
Data transition, SDR Mode
±50
and DDR Mode, 0˚ DCLK (Note 11)
ps (max)
tSU
Data to DCLK Set-Up Time
DDR Mode, 90˚ DCLK (Note 11)
667
tH
DCLK to Data Hold Time
DDR Mode, 90˚ DCLK (Note 11)
667
Input CLK+ Fall to Acquisition of
tAD
Sampling (Aperture) Delay
Data
1.3
ps
ps
ns
11 www.national.com
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| Páginas | Total 33 Páginas | |
| PDF Descargar | [ Datasheet ADC082500.PDF ] | |
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