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AD5665R Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD5665R
Beschreibung (AD5625x - AD5665x) nanoDACs
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 30 Seiten
AD5665R Datasheet, Funktion
www.DataSheet4U.com
Preliminary Technical Data
Quad, 12-/14-/16-Bit nanoDACs® with
5ppm/°C On-chip Ref, I2C Interface
AD5625R/AD5645R/AD5665R
AD5625/AD5665
FEATURES
Low power, smallest pin-compatible, quad nanoDACs
AD5625R/AD5645R/AD5665R
12-/14-/16 bits
On-chip 1.25 V/2.5 V, 5 ppm/°C reference.
AD5625/AD5665
12-/16 bits
External reference only
3 mm x 3 mm LFCSP and 14-lead TSSOP
2.7 V to 5.5 V power supply
Guaranteed monotonic by design
Power-on reset to zero scale/midscale
Per channel power-down
I2C-compatible serial interface supports standard (100 kHz),
fast (400 kHz), and high speed (3.4 MHz) modes
APPLICATIONS
Process control
Data acquisition systems
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
Programmable attenuators
GENERAL DESCRIPTION
The AD5625R/AD5645R/AD5665R, AD5625/AD5665
members of the nanoDAC family, are low power, quad, 12-, 14-,
16-bit buffered voltage-out DACs with/without an on-chip
reference. All devices operate from a single 2.7 V to 5.5 V
supply, are guaranteed monotonic by design and have an I2C-
compatible serial interface .
The AD5625R/AD5645R/AD5665R have an on-chip reference. The
AD56x5RBCPZ have a 1.25 V, 5 ppm/°C reference, giving a full-scale
output range of 2.5 V; the AD56x5RBRUZ have a 2.5 V, 5 ppm/°C
reference giving a full-scale output range of 5 V. The on-chip
reference is off at power-up, allowing the use of an external reference.
The internal reference is enabled via a software write. The AD5665
and AD5625 require an external reference voltage to set the
output range of the DAC.
The part incorporates a power-on reset circuit that ensures the
DAC output powers up to 0 V or midscale and remains there
Rev. PrA
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
VDD
AD5625R/AD5645R/AD5665R
GND
VREFIN/VREFOUT
1.25V/2.5V REF
ADDR1
ADDR2
SCL
SDA
INTERFACE
LOGIC
INPUT
REGISTER
DAC
REGISTER
STRING
DAC A
BUFFER
V O U TA
INPUT
REGISTER
DAC
REGISTER
STRING
DAC B
BUFFER
VOUTB
INPUT
REGISTER
DAC
REGISTER
STRING
DAC C
BUFFER
VOUTC
INPUT
REGISTER
DAC
REGISTER
POWER-ON
RESET
STRING
DAC D
BUFFER
P OW E R -D OW N
LOGIC
VO U TD
LDAC CLR
POR
NOTE. THE FOLLOWING PINS ARE AVAILABLE ONLY ON 14-PIN PACKAGE - ADDR2, LDAC, CLR, POR.
VDD
GND
VREFIN
AD5625/AD5665
ADDR1
ADDR2
SCL
SDA
INTERFACE
LOGIC
INPUT
REGISTER
DAC
REGISTER
STRING
DAC A
BUFFER
V O U TA
INPUT
REGISTER
DAC
REGISTER
STRING
DAC B
BUFFER
VOUTB
INPUT
REGISTER
DAC
REGISTER
STRING
DAC C
BUFFER
VOUTC
INPUT
REGISTER
DAC
REGISTER
POWER-ON
RESET
STRING
DAC D
BUFFER
P OW E R -D OW N
LOGIC
VO U TD
LDAC CLR
POR
NOTE. THE FOLLOWING PINS ARE AVAILABLE ONLY ON 14-PIN PACKAGE - ADDR2, LDAC, CLR, POR.
Figure 1. Functional Block Diagrams
until a valid write takes place. The part contains a per-channel
power-down feature that reduces the current consumption of
the device to 480 nA at 5 V and provides software-selectable
output loads while in power-down mode. The low power
consumption of this part in normal operation makes it ideally
suited to portable battery-operated equipment. The on-chip
precision output amplifier enables rail-to-rail output swing.
The AD5625R/AD5645R/AD5665R, AD5625/AD5665 use a 2-
wire I2C-compatible serial interface that operates in standard
(100 kHz), fast (400 kHz), and high speed (3.4 MHz) modes.
Table 1. Related Devices
Part No.
AD5624R/AD5644R/AD5664R
AD5624/AD5664
AD5627R/AD5647R/AD5667R
AD5627/5667,
AD5666
Description
Quad SPI 12-, 14-, 16-bit DACs,
with/without internal reference.
Dual I2C 12-, 14-,16-bit DACs,
with/without internal reference.
2.7 V to 5.5 V, Quad 16-bit DAC,
internal reference, SPI interface
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.






AD5665R Datasheet, Funktion
AD5625R/AD5645R/AD5665R, AD5625/AD5665
Preliminary Technical Data
I2C TIMING SPECIFICATIONS
VDD = 2.7 V to 5.5 V; all specifications TMIN to TMAX, fSCL = 3.4 MHz, unless otherwise noted.1
Table 5.
Parameter
fSCL3
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t11A
Conditions2
Standard mode
Fast mode
High speed mode, CB = 100 pF
High speed mode, CB = 400 pF
Standard mode
Fast mode
High speed mode, CB = 100 pF
High speed mode, CB = 400 pF
Standard mode
Fast mode
High speed mode, CB = 100 pF
High speed mode, CB = 400 pF
Standard mode
Fast mode
High speed mode
Standard mode
Fast mode
High speed mode, CB = 100 pF
High speed mode, CB = 400 pF
Standard mode
Fast mode
High speed mode
Standard mode
Fast mode
High speed mode
Standard mode
Limit at TMIN, TMAX
Min Max
100
400
3.4
1.7
4
0.6
60
120
4.7
1.3
160
320
250
100
10
0 3.45
0 0.9
0 70
0 150
4.7
0.6
160
4
0.6
160
4.7
Unit
KHz
KHz
MHz
MHz
μs
μs
μs
μs
ns
ns
ns
ns
ns
μs
μs
ns
ns
μs
μs
ns
μs
μs
ns
μs
Fast mode
Standard mode
Fast mode
High speed mode
Standard mode
Fast mode
High speed mode, CB = 100 pF
High speed mode, CB = 400 pF
Standard mode
Fast mode
High speed mode, CB = 100 pF
High speed mode, CB = 400 pF
Standard mode
Fast mode
High speed mode, CB = 100 pF
High speed mode, CB = 400 pF
Standard mode
1.3
4
0.6
160
10
20
10
20
10
20
1000
300
80
160
300
300
80
160
1000
300
40
80
1000
μs
μs
μs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Fast mode
High speed mode, CB = 100 pF
High speed mode, CB = 400 pF
10
20
300 ns
80 ns
160 ns
Description
Serial clock frequency
tHIGH, SCL high time
ns
ns
tLOW, SCL low time
tSU;DAT, data setup time
tHD;DAT, data hold time
tSU;STA, set-up time for a repeated start condition
tHD;STA, hold time (repeated) start condition
tBUF, bus free time between a stop and a start
condition
tSU;STO, setup time for a stop condition
tRDA, rise time of SDA signal
tFDA, fall time of SDA signal
tRCL, rise time of SCL signal
tRCL1, rise time of SCL signal after a repeated
start condition and after an acknowledge bit
Rev. PrA. | Page 6 of 32

6 Page









AD5665R pdf, datenblatt
AD5625R/AD5645R/AD5665R, AD5625/AD5665
Preliminary Technical Data
10
VDD = 3V
8 VREFOUT = 1.25V
TA = 25°C
6
4
2
0
–2
–4
–6
–8
–10
CODE
Figure 16. INL AD5665R,1.25V Internal Reference
4
VDD = 3V
3
VREFOUT = 1.25V
TA = 25°C
2
1
0
–1
–2
–3
–4
CODE
Figure 17. INL AD5645R, 1.25V Internal Reference
1.0
0.8
VDD = 3V
VREFOUT = 1.25V
0.6 TA = 25°C
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
0
500 1000 1500 2000 2500 3000 3500 4000
CODE
Figure 18. INL AD5625R,1.25V Internal Reference
1.0
VDD = 3V
0.8 VREFOUT = 1.25V
TA = 25°C
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
CODE
Figure 19. DNL AD5665R,1.25V Internal Reference
0.5
0.4
VDD = 3V
VREFOUT = 1.25V
0.3 TA = 25°C
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
CODE
Figure 20. DNL AD5645R,1.25V Internal Reference
0.20
0.15
VDD = 3V
VREFOUT = 1.25V
TA = 25°C
0.10
0.05
0
–0.05
–0.10
–0.15
–0.20
0
500 1000 1500 2000 2500 3000 3500
CODE
Figure 21. DNL AD5625R, 1.25V Internal Reference
4000
Rev. PrA. | Page 12 of 32

12 Page





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