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AD5373 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD5373
Beschreibung (AD5372 / AD5373) Voltage-Output DACs
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 25 Seiten
AD5373 Datasheet, Funktion
www.DataSheet4U.com
Preliminary Technical Data
32-Channel, 16/14, Serial Input,
Voltage-Output DACs
AD5372/AD5373
FEATURES
32-channel DAC in 56-LFCSP and 64-LQFP
AD5372 Guaranteed monotonic to 16 bits
AD5373 Guaranteed monotonic to 14 bits
Maximum output voltage span of 4 × VREF (20 V)
Nominal output voltage range of -4 V to +8 V
Multiple, independent output spans available
System calibration function allowing user-programmable
offset and gain
Channel grouping and addressing features
Thermal Monitoring Function
DSP/microcontroller-compatible serial interface
2.5 V to 5.5 V JEDEC-compliant digital levels
Power-on reset
Digital reset (RESET)
Clear function to user-defined SIGGND (CLR pin)
Simultaneous update of DAC outputs (LDAC pin)
APPLICATIONS
Level setting in automatic test equipment (ATE)
Variable optical attenuators (VOA)
Optical switches
Industrial control systems
Instrumentation
FUNCTIONAL BLOCK DIAGRAM
DVCC VDD VSS AGND DNGD
LDAC
SYNC
SDI
SCLK
SDO
BUSY
RESET
CLR
CONTROL
REGISTER
n
SERIAL
INTERFACE
STATE
MACHINE
n
POWER-ON
RESET
AD5372/
AD5373
n = 16 FOR AD5372
n = 14 FOR AD5373
8 A/B SELECT 8
REGISTER
TO
MUX 2's
n
n
X1 REGISTER
n A/B
MUX
nn
M REGISTER
n C REGISTER
n
······ ······ ······ ······
n
n
X1 REGISTER
nn
M REGISTER
n C REGISTER
n A/B
MUX
n
8 A/B SELECT 8
TO
REGISTER
MUX 2's
n
n
X1 REGISTER
n A/B
MUX
nn
M REGISTER
n C REGISTER
n
······ ······ ······ ······
n
n
X1 REGISTER
nn
M REGISTER
n
C REGISTER
n A/B
MUX
n
14 OFS0 n
REGISTER
OFFSET
DAC 0
X2A REGISTER
X2B REGISTER
·
·
·
·
·
·
X2A REGISTER
X2B REGISTER
MUX n
2
·
·
·
·
·
·
MUX n
2
DAC 0 n
REGISTER
·
·
·
·
·
·
DAC 7 n
REGISTER
DAC 0
···
···
DAC 7
BUFFER
GROUP 0
BUFFER
OUTPUT BUFFER
AND POWER
DOWN CONTROL
·
··
··
·
OUTPUT BUFFER
AND POWER
DOWN CONTROL
14 OFS1 n
REGISTER
OFFSET
DAC 1
X2A REGISTER
X2B REGISTER
·
·
·
·
·
·
X2A REGISTER
X2B REGISTER
MUX n
2
·
·
·
·
·
·
MUX n
2
DAC 0 n
REGISTER
·
·
·
·
·
·
DAC 7 n
REGISTER
DAC 0
·
···
··
DAC 7
BUFFER
GROUP 1
OUTPUT BUFFER
AND POWER
DOWN CONTROL
·
··
··
·
OUTPUT BUFFER
AND POWER
DOWN CONTROL
VREF1 SUPPLIES
GROUP 2 TO GROUP 3 GROUP 1 TO 3
ARE IDENTICAL TO GROUP 1
5 372-000 1B
Figure 1.
AD5372/AD5373—Protected by U.S. Patent No. 5,969,657; other patents pending
SIGGND2
SIGGND3
VREF0
VOUT0
VOUT1
VOUT2
VOUT3
VOUT4
VOUT5
VOUT6
VOUT7
SIGGND0
VREF1
VOUT8
VOUT9
VOUT10
VOUT11
VOUT12
VOUT13
VOUT14
VOUT15
SIGGND1
VOUT16
TO
VOUT31
Rev. PrF
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703 © 2006 Analog Devices, Inc. All rights reserved.






AD5373 Datasheet, Funktion
AD5372/AD5373
Preliminary Technical Data
TIMING CHARACTERISTICS
DVCC = 2.3 V to 5.5 V; VDD = 8 V to 16.5 V; VSS = −4.5 V to −16.5 V; VREF = 3 V; AGND = DGND = SIGGND = 0 V;
RL = Open Circuit; Gain (m), Offset(c) and DAC Offset registers at default value; all specifications TMIN to TMAX, unless otherwise noted.
SPI INTERFACE (Figure 4 and Figure 5)
Parameter1, 2, 3
t1
t2
t3
t4
t5
t6
t7
t8
t93
t10
Limit at TMIN, TMAX
20
8
8
11
20
10
5
5
42
1.25
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
µs max
Description
SCLK Cycle Time.
SCLK High Time.
SCLK Low Time.
SYNC Falling Edge to SCLK Falling Edge Setup Time.
Minimum SYNC High Time.
24th SCLK Falling Edge to SYNC Rising Edge.
Data Setup Time.
Data Hold Time.
SYNC Rising Edge to BUSY Falling Edge.
BUSY Pulse Width Low (Single-Channel Update.) See Table 7.
t11 500
t12 20
ns max
ns min
Single-Channel Update Cycle Time
24th SCLK Falling Edge to LDAC Falling Edge.
t13 10
ns min
LDAC Pulse Width Low.
t14 3
µs max
BUSY Rising Edge to DAC Output Response Time.
t15 0
ns min
BUSY Rising Edge to LDAC Falling Edge.
t16 3
µs max
LDAC Falling Edge to DAC Output Response Time.
t17 20/30
t18 125
µs typ/max DAC Output Settling Time.
ns max
CLR/RESET Pulse Activation Time.
t19 330
ns min
RESET Pulse Width Low.
t20 400
µs max
RESET Time Indicated by BUSY Low.
t21 270
ns min
Minimum SYNC High Time in Readback Mode.
t225 25
ns max
SCLK Rising Edge to SDO Valid.
1 Guaranteed by design and characterization, not production tested.
2 All input signals are specified with tr = tf = 2 ns (10% to 90% of VCC) and timed from a voltage level of 1.2 V.
3 See Figure 4 and Figure 5.
4 This is measured with the load circuit of Figure 2.
5 This is measured with the load circuit of Figure 3.
VCC
TO
OUTPUT
PIN
RL 2.2k
CL 50pF
VOL
200µA
TO
OUTPUT
PIN
CL
50pF
200µA
IOL
IOL
VOH(min) - VOL (max)
2
Figure 2. Load Circuit for BUSY Timing Diagram
Figure 3. Load Circuit for SDO Timing Diagram
Rev. PrF| Page 6 of 25

6 Page









AD5373 pdf, datenblatt
AD5372/AD5373
Preliminary Technical Data
FUNCTIONAL DESCRIPTION
DAC ARCHITECTURE—GENERAL
The ADAD5372/AD5373 contains 32 DAC channels and 32
output amplifiers in a single package. The architecture of a
single DAC channel consists of a 16-bit (AD5372) or 14-bit
(AD5373) resistor-string DAC followed by an output buffer
amplifier. The resistor-string section is simply a string of
resistors, each of value R, from VREF to AGND. This type of
architecture guarantees DAC monotonicity. The 16-bit
(AD5372) or 14-bit (AD5373) binary digital code loaded to the
DAC register determines at which node on the string the
voltage is tapped off before being fed into the output amplifier.
The output amplifier multiplies the DAC out voltage by 4. The
output span is 12 V with a 3 V reference and 20 V with a 5 V
reference.
CHANNEL GROUPS
The 32 DAC channels of the AD5372/AD5373 are arranged
into four groups of 8 channels. The eight DACs of Group 0
derive their reference voltage from VREF0. Group 1 to Group 3
derive their reference voltage from VREF1. Each group has its
own signal ground pin.
Table 6. AD5372(AD5373) Registers
Register Name
X1A (group)(channel)
X1B (group) (channel)
M (group) (channel)
C (group) (channel)
X2A (group)(channel)
Word Length (Bits)
16(14)
16(14)
16(14)
16(14)
16(14)
X2B (group) (channel) 16(14)
DAC (group) (channel)
OFS0
OFS1
Control
14
14
3
A/B Select 0
A/B Select 1
A/B Select 2
A/B Select 3
8
8
8
8
Description
Input data register A, one for each DAC channel.
Input data register B, one for each DAC channel.
Gain trim registers, one for each DAC channel.
Offset trim registers, one for each DAC channel.
Output data register A, one for each DAC channel. These registers store the final,
calibrated DAC data after gain and offset trimming. They are not readable, nor directly
writable.
Output data register B, one for each DAC channel. These registers store the final,
calibrated DAC data after gain and offset trimming. They are not readable, nor directly
writable.
Data registers from which the DACs take their final input data. The DAC registers are
updated from the X2A or X2B registers. They are not readable, nor directly writable.
Offset DAC 0 data register, sets offset for Group 0.
Offset DAC 1 data register, sets offset for Groups 1 to 3.
Bit 2 = A/B. 0 = global selection of X1A input data registers. 1 = X1B registers.
Bit 1 = Enable Temp Shutdown. 0 = disable temp shutdown. 1 = enable.
Bit 0 = Soft Power Down. 0 = soft power up. 1 = soft power down.
Each bit in this register determines if a DAC in Group 0 takes its data from register
X2A or X2B (0 = X2A, 1 = X2B)
Each bit in this register determines if a DAC in Group 1 takes its data from register
X2A or X2B (0 = X2A, 1 = X2B)
Each bit in this register determines if a DAC in Group 2 takes its data from register
X2A or X2B (0 = X2A, 1 = X2B)
Each bit in this register determines if a DAC in Group 3 takes its data from register
X2A or X2B (0 = X2A, 1 = X2B)
Rev. PrF| Page 12 of 25

12 Page





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