AD5372 Datasheet PDF - Analog Devices
| Part Number | AD5372 | |
| Description | (AD5372 / AD5373) Voltage-Output DACs | |
| Manufacturers | Analog Devices | |
| Logo |  |
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Preliminary Technical Data
32-Channel, 16/14, Serial Input,
Voltage-Output DACs
AD5372/AD5373
FEATURES
32-channel DAC in 56-LFCSP and 64-LQFP
AD5372 Guaranteed monotonic to 16 bits
AD5373 Guaranteed monotonic to 14 bits
Maximum output voltage span of 4 × VREF (20 V)
Nominal output voltage range of -4 V to +8 V
Multiple, independent output spans available
System calibration function allowing user-programmable
offset and gain
Channel grouping and addressing features
Thermal Monitoring Function
DSP/microcontroller-compatible serial interface
2.5 V to 5.5 V JEDEC-compliant digital levels
Power-on reset
Digital reset (RESET)
Clear function to user-defined SIGGND (CLR pin)
Simultaneous update of DAC outputs (LDAC pin)
APPLICATIONS
Level setting in automatic test equipment (ATE)
Variable optical attenuators (VOA)
Optical switches
Industrial control systems
Instrumentation
FUNCTIONAL BLOCK DIAGRAM
DVCC VDD VSS AGND DNGD
LDAC
SYNC
SDI
SCLK
SDO
BUSY
RESET
CLR
CONTROL
REGISTER
n
SERIAL
INTERFACE
STATE
MACHINE
n
POWER-ON
RESET
AD5372/
AD5373
n = 16 FOR AD5372
n = 14 FOR AD5373
8 A/B SELECT 8
REGISTER
TO
MUX 2's
n
n
X1 REGISTER
n A/B
MUX
nn
M REGISTER
n C REGISTER
n
······ ······ ······ ······
n
n
X1 REGISTER
nn
M REGISTER
n C REGISTER
n A/B
MUX
n
8 A/B SELECT 8
TO
REGISTER
MUX 2's
n
n
X1 REGISTER
n A/B
MUX
nn
M REGISTER
n C REGISTER
n
······ ······ ······ ······
n
n
X1 REGISTER
nn
M REGISTER
n
C REGISTER
n A/B
MUX
n
14 OFS0 n
REGISTER
OFFSET
DAC 0
X2A REGISTER
X2B REGISTER
·
·
·
·
·
·
X2A REGISTER
X2B REGISTER
MUX n
2
·
·
·
·
·
·
MUX n
2
DAC 0 n
REGISTER
·
·
·
·
·
·
DAC 7 n
REGISTER
DAC 0
···
···
DAC 7
BUFFER
GROUP 0
BUFFER
OUTPUT BUFFER
AND POWER
DOWN CONTROL
·
··
··
·
OUTPUT BUFFER
AND POWER
DOWN CONTROL
14 OFS1 n
REGISTER
OFFSET
DAC 1
X2A REGISTER
X2B REGISTER
·
·
·
·
·
·
X2A REGISTER
X2B REGISTER
MUX n
2
·
·
·
·
·
·
MUX n
2
DAC 0 n
REGISTER
·
·
·
·
·
·
DAC 7 n
REGISTER
DAC 0
·
···
··
DAC 7
BUFFER
GROUP 1
OUTPUT BUFFER
AND POWER
DOWN CONTROL
·
··
··
·
OUTPUT BUFFER
AND POWER
DOWN CONTROL
VREF1 SUPPLIES
GROUP 2 TO GROUP 3 GROUP 1 TO 3
ARE IDENTICAL TO GROUP 1
5 372-000 1B
Figure 1.
AD5372/AD5373—Protected by U.S. Patent No. 5,969,657; other patents pending
SIGGND2
SIGGND3
VREF0
VOUT0
VOUT1
VOUT2
VOUT3
VOUT4
VOUT5
VOUT6
VOUT7
SIGGND0
VREF1
VOUT8
VOUT9
VOUT10
VOUT11
VOUT12
VOUT13
VOUT14
VOUT15
SIGGND1
VOUT16
TO
VOUT31
Rev. PrF
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703 © 2006 Analog Devices, Inc. All rights reserved.
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Preliminary Technical Data
AD5372/AD5373
Parameter
POWER REQUIREMENTS
DVCC
VDD
VSS
Power Supply Sensitivity2
∆ Full Scale/∆ VDD
∆ Full Scale/∆ VSS
∆ Full Scale/∆ VCC
DICC
IDD
ISS
Power Dissipation
Power Dissipation Unloaded (P)
Junction Temperature3
AD53721 AD53731 Unit
B Version B Version
Test Conditions/Comments2
2.3/5.5
2.3/5.5
V min/max
8/16.5
8/16.5
V min/max
−4.5/−16.5 −4.5/−16.5 V min/max
−75 −75 dB typ
−75 −75 dB typ
−90 −90 dB typ
2
2
mA max
VCC = 5.5 V, VIH = VCC, VIL = GND.
14
14
mA max
Outputs unloaded.
14
14
mA max
Outputs unloaded.
350 350 mW
130
130
°C max
TJ = TA + PTOTAL × θJ.
1 Temperature range for B Version: −40°C to +85°C. Typical specifications are at 25°C.
2 Guaranteed by design and characterization, not production tested.
3 Where θJ represents the package thermal impedance.
AC CHARACTERISTICS
DVCC = 2.5 V; VDD = 15 V; VSS = −15 V; VREF = 3 V; AGND = DGND = SIGGND = 0 V; CL = 200pF; RL = 10 kΩ;
Gain (m), Offset(c) and DAC Offset registers at default value; all specifications TMIN to TMAX, unless otherwise noted.
Table 3. AC Characteristics
Parameter
AD5372/
AD5373
DYNAMIC PERFORMANCE1
Output Voltage Settling Time
20
30
Slew Rate
1
Digital-to-Analog Glitch Energy
20
Glitch Impulse Peak Amplitude
10
Channel-to-Channel Isolation
100
DAC-to-DAC Crosstalk
40
10
Digital Crosstalk
0.1
Digital Feedthrough
1
Output Noise Spectral Density @ 10 kHz 250
1Guaranteed by design and characterization. Not production tested
Unit Test Conditions/Comments
µs typ
µs max
V/µs typ
nV-s typ
mV max
dB typ
nV-s typ
nV-s typ
nV-s typ
nV-s typ
nV/(Hz)1/2 typ
Full-scale change
DAC latch contents alternately loaded with all 0s and all 1s.
VREF(+) = 2 V p-p, 1 kHz.
Between DACs in the same group.
Between DACs from different groups.
Effect of input bus activity on DAC output under test.
VREF = 0 V.
Rev. PrF | Page 5 of 25
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| Information | Total 25 Pages | |
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