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PDF AD5363 Data sheet ( Hoja de datos )
| Número de pieza | AD5363 | |
| Descripción | (AD5362 / AD5363) Voltage-Output DAC | |
| Fabricantes | Analog Devices | |
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Preliminary Technical Data
8-Channel, 16/14-Bit,
Serial Input, Voltage-Output DAC
AD5362/AD5363
FEATURES
8-channel DAC in 52-LQFP and 56-LFCSP
Guaranteed monotonic to 16/14 bits
Nominal output voltage range of -10 V to +10 V
Multiple output spans available
Temperature Monitoring Function
Channel Monitoring Multiplexer
GPIO Function
System calibration function allowing user-programmable
offset and gain
Channel grouping and addressing features
Data error checking feature
SPI compatible serial interface
2.5 V to 5.5 V JEDEC-compliant digital levels
Power-on reset
Digital reset (RESET)
Clear function to user-defined SIGGND (CLR pin)
Simultaneous update of DAC outputs (LDAC pin)
APPLICATIONS
Instrumentation
Industrial Control System
PLC Analog I/O Cards
Level setting in automatic test equipment (ATE)
Variable optical attenuators (VOA)
Precision Medical Instruments
TEMP_OUT
PEC
MON_IN0
MON_IN1
MON_OUT
GPIO
BIN/2SCOMP
SYNC
SDI
SCLK
SDO
BUSY
RESET
CLR
FUNCTIONAL BLOCK DIAGRAM
DVCC VDD VSS AGND DNGD
LDAC
TEMP
SENSOR
CONTROL
REGISTER
8
VOUT0 -
VOUT7
MUX
6
GPIO
REGISTER
2
SERIAL
INTERFACE
AD5362, n = 16
AD5363, n = 14
4 A/B SELECT 4
REGISTER
TO
MUX 2's
n
n
X1 REGISTER
n A/B
MUX
nn
M REGISTER
n C REGISTER
n
······ ······ ······ ······
n
n
X1 REGISTER
nn
M REGISTER
n
C REGISTER
n A/B
MUX
n
STATE
MACHINE
n
POWER-ON
RESET
AD5362/
AD5363
4 A/B SELECT 4
TO
REGISTER
MUX 2's
n
n
X1 REGISTER
n A/B
MUX
nn
M REGISTER
n
n
C REGISTER
······ ······ ······ ······
n
n
X1 REGISTER
nn
M REGISTER
n
C REGISTER
n A/B
MUX
n
14 OFS0 14 OFFSET
REGISTER
DAC 0
X2A REGISTER
X2B REGISTER
·
·
·
·
·
·
X2A REGISTER
X2B REGISTER
MUX n
2
·
·
·
·
·
·
MUX n
2
DAC 0 n
REGISTER
·
·
·
·
·
·
DAC 3 n
REGISTER
DAC 0
·
···
··
DAC 3
14 OFS1 14 OFFSET
REGISTER
DAC 1
X2A REGISTER
X2B REGISTER
·
·
·
·
·
·
X2A REGISTER
X2B REGISTER
MUX n
2
·
·
·
·
·
·
MUX n
2
DAC 0 n
REGISTER
·
·
·
·
·
·
DAC 3 n
REGISTER
DAC 0
·
···
··
DAC 3
BUFFER
GROUP 0
BUFFER
OUTPUT BUFFER
AND POWER
DOWN CONTROL
·
···
··
OUTPUT BUFFER
AND POWER
DOWN CONTROL
GROUP 1
BUFFER
OUTPUT BUFFER
AND POWER
DOWN CONTROL
··
··
··
OUTPUT BUFFER
AND POWER
DOWN CONTROL
5362-0001B
VREF0
VOUT0
VOUT1
VOUT2
VOUT3
SIGGND0
VREF1
VOUT4
VOUT5
VOUT6
VOUT7
SIGGND1
Figure 1.
AD5362/AD5363—Protected by U.S. Patent No. 5,969,657; other patents pending
Rev. PrF
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703 © 2006 Analog Devices, Inc. All rights reserved.
1 page  
Preliminary Technical Data
Parameter
POWER REQUIREMENTS
DVCC
VDD
VSS
Power Supply Sensitivity2
∆ Full Scale/∆ VDD
∆ Full Scale/∆ VSS
∆ Full Scale/∆ VCC
DICC
IDD
ISS
Power Dissipation
Power Dissipation Unloaded (P)
Junction Temperature3
B Version 1 Unit
Test Conditions/Comments2
2.3/5.5
8/16.5
−4.5/−16.5
V min/max
V min/max
V min/max
−75 dB typ
−75 dB typ
−90 dB typ
2
mA max
VCC = 5.5 V, VIH = VCC, VIL = GND.
5
mA max
Outputs unloaded.
5
mA max
Outputs unloaded.
350 mW
130
°C max
TJ = TA + PTOTAL × θJ.
1 Temperature range for B Version: −40°C to +85°C. Typical specifications are at 25°C.
2 Guaranteed by design and characterization, not production tested.
3 Where θJ represents the package thermal impedance.
AD5362/AD5363
AC CHARACTERISTICS
DVCC = 2.5 V; VDD = 15 V; VSS = −15 V; VREF = 3 V; AGND = DGND = SIGGND = 0 V; CL = 200pF; RL = 10 kΩ;
Gain (m), Offset(c) and DAC Offset registers at default value; all specifications TMIN to TMAX, unless otherwise noted.
Table 3. AC Characteristics
Parameter
B Version
DYNAMIC PERFORMANCE1
Output Voltage Settling Time
20
30
Slew Rate
1
Digital-to-Analog Glitch Energy
20
Glitch Impulse Peak Amplitude
10
Channel-to-Channel Isolation
100
DAC-to-DAC Crosstalk
40
10
Digital Crosstalk
0.1
Digital Feedthrough
1
Output Noise Spectral Density @ 10 kHz 250
1Guaranteed by design and characterization. Not production tested
Unit Test Conditions/Comments
µs typ
µs max
V/µs typ
nV-s typ
mV max
dB typ
nV-s typ
nV-s typ
nV-s typ
nV-s typ
nV/(Hz)1/2 typ
Full-scale change
DAC latch contents alternately loaded with all 0s and all 1s.
VREF = 2 V p-p, 1 kHz.
Between DACs in the same group.
Between DACs from different groups.
Effect of input bus activity on DAC output under test.
VREF = 0 V.
Rev. PrF | Page 5 of 25
5 Page 
Preliminary Technical Data
TERMINOLOGY
Relative Accuracy
Relative accuracy, or endpoint linearity, is a measure of the
maximum deviation from a straight line passing through the
endpoints of the DAC transfer function. It is measured after
adjusting for zero-scale error and full-scale error and is
expressed in least significant bits (LSB).
Differential Nonlinearity
Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of 1 LSB maximum
ensures monotonicity.
Zero-Scale Error
Zero-scale error is the error in the DAC output voltage when all
0s are loaded into the DAC register.
Zero-scale error is a measure of the difference between VOUT
(actual) and VOUT (ideal) expressed in mV. Zero-scale error is
mainly due to offsets in the output amplifier.
Full-Scale Error
Full-scale error is the error in DAC output voltage when all 1s
are loaded into the DAC register.
Full-scale error is a measure of the difference between VOUT
(actual) and VOUT (ideal) expressed in mV. It does not include
zero-scale error.
Gain Error Gain error is the difference between full-scale error
and zero-scale error. It is expressed in mV.
Gain Error = Full-Scale Error − Zero-Scale Error
VOUT Temperature Coefficient
This includes output error contributions from linearity, offset,
and gain drift.
DC Output Impedance
DC output impedance is the effective output source resistance.
It is dominated by package lead resistance.
AD5362/AD5363
DC Crosstalk
The DAC outputs are buffered by op amps that share common
VDD and VSS Vpower supplies. If the dc load current changes in
one channel (due to an update), this can result in a further dc
change in one or more channel outputs. This effect is more
significant at high load currents and reduces as the load
currents are reduced. With high impedance loads, the effect is
virtually immeasurable. Multiple VDD and VSS terminals are
provided to minimize dc crosstalk.
Output Voltage Settling Time
The amount of time it takes for the output of a DAC to settle to
a specified level for a full-scale input change.
Digital-to-Analog Glitch Energy
The amount of energy injected into the analog output at the
major code transition. It is specified as the area of the glitch in
nV-s. It is measured by toggling the DAC register data between
0x1FFF and 0x2000.
Channel-to-Channel Isolation
Channel-to-channel isolation refers to the proportion of input
signal from one DAC’s reference input that appears at the
output of another DAC operating from another reference. It is
expressed in dB and measured at midscale.
DAC-to-DAC Crosstalk
DAC-to-DAC crosstalk is the glitch impulse that appears at the
output of one converter due to both the digital change and
subsequent analog output change at another converter. It is
specified in nV-s.
Digital Crosstalk
The glitch impulse transferred to the output of one converter
due to a change in the DAC register code of another converter is
defined as the digital crosstalk and is specified in nV-s.
Digital Feedthrough
When the device is not selected, high frequency logic activity
on the device’s digital inputs can be capacitively coupled both
across and through the device to show up as noise on the
VOUT pins. It can also be coupled along the supply and ground
lines. This noise is digital feedthrough.
Output Noise Spectral Density
Output noise spectral density is a measure of internally
generated random noise. Random noise is characterized as a
spectral density (voltage per √Hz). It is measured by loading all
DACs to midscale and measuring noise at the output. It is
measured in nV/(Hz)1/2
Rev. PrF | Page 11 of 25
11 Page | ||
| Páginas | Total 25 Páginas | |
| PDF Descargar | [ Datasheet AD5363.PDF ] | |
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