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ADF4360-8 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer ADF4360-8
Beschreibung Integrated Synthesizer and VCO
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 25 Seiten
ADF4360-8 Datasheet, Funktion
Data Sheet
Integrated Synthesizer and VCO
ADF4360-8
FEATURES
Output frequency range: 65 MHz to 400 MHz
3.0 V to 3.6 V power supply
1.8 V logic compatibility
Integer-N synthesizer
Programmable output power level
3-wire serial interface
Digital lock detect
Hardware and software power-down mode
APPLICATIONS
System clock generation
Test equipment
Wireless LANs
CATV equipment
GENERAL DESCRIPTION
The ADF4360-8 is an integrated integer-N synthesizer and
voltage-controlled oscillator (VCO). The ADF4360-8 center
frequency is set by external inductors. This allows a frequency
range of between 65 MHz to 400 MHz.
Control of all the on-chip registers is through a simple 3-wire
interface. The device operates with a power supply ranging
from 3.0 V to 3.6 V and can be powered down when not in use.
FUNCTIONAL BLOCK DIAGRAM
AVDD
DVDD
RSET
CE
ADF4360-8
REFIN
14-BIT R
COUNTER
CLK
DATA
LE
24-BIT
DATA REGISTER
24-BIT
FUNCTION
LATCH
LOCK
DETECT
MULTIPLEXER
MUTE
CHARGE
PUMP
PHASE
COMPARATOR
MUXOUT
CP
VVCO
VTUNE
L1
L2
CC
CN
13-BIT B
COUNTER
N=B
VCO
CORE
OUTPUT
STAGE
RFOUTA
RFOUTB
AGND
DGND
CPGND
Figure 1.
Rev. D
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ADF4360-8 Datasheet, Funktion
Data Sheet
ADF4360-8
TIMING CHARACTERISTICS1
AVDD = DVDD = VVCO = 3.3 V ± 10%; AGND = DGND = 0 V; 1.8 V and 3 V logic levels used; TA = TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter
t1
t2
t3
t4
t5
t6
t7
Limit at TMIN to TMAX (B Version)
20
10
10
25
25
10
20
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
1 Refer to the Power-Up section for the recommended power-up procedure for this device.
Test Conditions/Comments
LE setup time
DATA to CLOCK setup time
DATA to CLOCK hold time
CLOCK high duration
CLOCK low duration
CLOCK to LE setup time
LE pulse width
CLOCK
DATA
DB23 (MSB)
t2 t3
DB22
t4 t5
DB2
DB1
(CONTROL BIT C2)
LE
t1
LE
Figure 2. Timing Diagram
DB0 (LSB)
(CONTROL BIT C1)
t7
t6
Rev. D | Page 5 of 24

6 Page









ADF4360-8 pdf, datenblatt
Data Sheet
Lock Detect
MUXOUT can be programmed for one type of lock detect. Dig-
ital lock detect is active high. When LDP in the R counter latch
is set to 0, digital lock detect is set high when the phase error on
three consecutive phase detector cycles is less than 15 ns.
With LDP set to 1, five consecutive cycles of less than 15 ns
phase error are required to set the lock detect. It stays set high
until a phase error of greater than 25 ns is detected on any
subsequent PD cycle.
INPUT SHIFT REGISTER
The digital section of the ADF4360-8 includes a 24-bit input
shift register, a 14-bit R counter, and an 18-bit N counter
comprised of a 5-bit A counter and a 13-bit B counter. Data is
clocked into the 24-bit shift register on each rising edge of CLK.
The data is clocked in MSB first. Data is transferred from the
shift register to one of four latches on the rising edge of LE. The
destination latch is determined by the state of the two control
bits (C2, C1) in the shift register. The two LSBs, DB1 and DB0,
are shown in Figure 2.
The truth table for these bits is shown in Table 5. Table 6 shows
a summary of how the latches are programmed. Note that the
test modes latch is used for factory testing and should not be
programmed by the user.
Table 5. C2 and C1 Truth Table
Control Bits
C2 C1 Data Latch
0 0 Control Latch
0 1 R Counter
1 0 N Counter (B)
1 1 Test Modes Latch
VCO
The VCO core in the ADF4360-8 uses eight overlapping bands,
as shown in Figure 19, to allow a wide frequency range to be
covered without a large VCO sensitivity (KV) and resultant poor
phase noise and spurious performance.
ADF4360-8
The correct band is chosen automatically by the band select logic
at power-up or whenever the N counter latch is updated. It is
important that the correct write sequence be followed at power-
up. This sequence is
1. R counter latch
2. Control latch
3. N counter latch
During band select, which takes five PFD cycles, the VCO VTUNE
is disconnected from the output of the loop filter and connected
to an internal reference voltage.
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
80 85 90 95 100 105 110 115
FREQUENCY (MHz)
Figure 19. Frequency vs. VTUNE, ADF4360-8, L1 and L2 = 270 nH
The R counter output is used as the clock for the band select
logic and should not exceed 1 MHz. A programmable divider is
provided at the R counter input to allow division by 1, 2, 4, or 8,
and is controlled by the BSC1 bit and the BSC2 bit in the R
counter latch. Where the required PFD frequency exceeds
1 MHz, the divide ratio should be set to allow enough time for
correct band selection.
After band selection, normal PLL action resumes. The value of
KV is determined by the value of inductors used (see the Choos-
ing the Correct Inductance Value section). The ADF4360-8
contains linearization circuitry to minimize any variation of the
product of ICP and KV.
The operating current in the VCO core is programmable in four
steps: 2.5 mA, 5 mA, 7.5 mA, and 10 mA. This is controlled by
the PC1 bit and the PC2 bit in the control latch.
Rev. D | Page 11 of 24

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