PDF AD1981BL Data sheet ( Hoja de datos )

Número de pieza	AD1981BL
Descripción	AC 97 SoundMAX Codec
Fabricantes	Analog Devices
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No Preview Available ! www.DataSheet4U.com AC ’97 SoundMAX® Codec AD1981BL AC ’97 2.3 COMPATIBLE FEATURES ENHANCED FEATURES S/PDIF output, 20-bit data format, supporting Stereo MIC preamplifier support 48 kHz and 44.1 kHz sample rates Built-in digital equalizer function for optimized Integrated stereo headphone amplifier speaker sound Variable sample rate audio Full-duplex variable sample rates from 7040 Hz to External audio power-down control 48 kHz with 1 Hz resolution >90 dB dynamic range Jack sense pins for automatic output switching Stereo full-duplex codec Software-programmed VREFOUT output for biasing 20-bit PCM DAC microphone and external power amplifier 3 analog line-level stereo inputs for line-in, AUX, and CD Low power 3.3 V operation for analog and digital supplies Mono line-level phone input Multiple codec configuration options Dual MIC input with built-in programmable preamplifier High quality CD input with ground sense Mono output for speakerphone or internal speaker power management support 48-lead LQFP package, Pb-free available FUNCTIONAL BLOCK DIAGRAM VREFOUT VREF XTL_OUT XTL_IN SPDIF MIC1 MIC2 PHONE_IN CD_L CD_GND CD_R AUX_L AUX_R LINE_IN_L LINE_IN_R AD1981BL MIC PREAMP G G CD DIFF AMP MONO_OUT MA G VOLTAGE REFERENCE CODEC CORE GM GM PCM L/R ADC RATE 16-BIT Σ-∆ ADC 16-BIT Σ-∆ ADC SPDIF TX PLL ID0 ID1 GM GM 16-BIT Σ-∆ ADC 16-BIT Σ-∆ ADC ADC AND DAC SLOT LOGIC RESET SYNC BIT_CLK M GA 20-BIT Σ-∆ DAC EQ SDATA_OUT HP_OUT_L HP M A LINE_OUT_L MZ A LINE_OUT_R MZ A HP_OUT_R HP M A GA GA GA GA MM MM M GA GA GA GA MM MM M GA 20-BIT Σ-∆ DAC G = GAIN A = ATTENUATION M = MUTE Z = HIGH Z PCM FRONT DAC RATE M EQ SDATA_IN AC '97 CONTROL REGISTERS ANALOG MIXING CONTROL LOGIC EAPD Figure 1. JS0 JS1 EAPD Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 © 2005 Analog Devices, Inc. All rights reserved. 1 page Parameter Low Level Output Voltage (VOL), IOL = 2 mA Input Leakage Current Output Leakage Current POWER SUPPLY Power Supply Range (AVDD and DVDD) Power Dissipation Analog Supply Current—3.3 V (AVDD) Digital Supply Current—3.3 V (DVDD) Power Supply Rejection (100 mV p-p Signal at 1 kHz)1 (At Both Analog and Digital Supply Pins, Both ADCs and DACs) CLOCK SPECIFICATIONS1 Input Clock Frequency Recommended Clock Duty Cycle 1 Guaranteed but not tested. 2 Measurements reflect main ADC. POWER-DOWN STATES Values presented with VREFOUT not loaded. Table 3. Parameter Fully Active ADC DAC ADC + DAC Mixer ADC + Mixer DAC + Mixer ADC + DAC + Mixer Standby Headphone Standby Set Bits No Bits Value PR0 PR1 PR1, PR0 PR2 PR2, PR0 PR2, PR1 PR2, PR1, PR0 PR5, PR4, PR3, PR2, PR1, PR0 PR6 AD1981BL Min Typ Max Unit 0.1 × DVDD V −10 +10 µA −10 +10 µA 3.0 3.47 2.87 39 48 40 V mW mA mA dB 24.576 40 50 60 MHz % DVDD Typ 47.76 40.1 32.8 13.2 47.7 40 32.77 13.9 0 47.7 AVDD Typ 38.9 34.39 26.3 20.55 19.39 14.86 6.39 1.15 0 32 Unit mA mA mA mA mA mA mA mA mA mA TIMING PARAMETERS Guaranteed over operating temperature range. Table 4. Parameter RESET Active Low Pulse Width RESET Inactive to BIT_CLK Start-Up Delay SYNC Active High Pulse Width SYNC Low Pulse Width SYNC Inactive to BIT_CLK Start-Up Delay BIT_CLK Frequency BIT_CLK Frequency Accuracy BIT_CLK Period BIT_CLK Output Jitter1, 2, 3 BIT_CLK High Pulse Width BIT_CLK Low Pulse Width SYNC Frequency Symbol tRST_LOW tRST2CLK tSYNC_HIGH tSYNC_LOW tSYNC2CLK tCLK_PERIOD tCLK_HIGH tCLK_LOW Rev. A \| Page 5 of 32 Min 162.8 162.8 32.56 32.56 Typ 1.0 1.3 19.5 12.288 81.4 750 42 38 48.0 Max ±1 2000 48.84 Unit ms ns µs µs ns MHz ppm ns ps ns ns kHz 5 Page AD1981BL Pin No. 22 23 24 35 36 37 39 41 FILTER/REFERENCE2 27 28 29 30 31 32 POWER AND GROUND SIGNALS 1 4 7 9 25 26 38 40 43 44 34 33 NO CONNECTS 12 42 Mnemonic MIC2 LINE_IN_L LINE_IN_R LINE_OUT_L LINE_OUT_R MONO_OUT HP_OUT_L HP_OUT_R I/O Description I Microphone 2 Input (Mono) or Right Channel when 2-Channel Mode Selected (Stereo MIC). I Line-In Left Channel. I Line-In Right Channel. O Line-Out (Front) Left Channel. O Line-Out (Front) Right Channel. O Monaural Output to Telephony Subsystem Speaker Phone. O Headphone Left-Channel Output. O Headphone Right-Channel Output. VREF VREFOUT AFILT1 AFILT2 AFILT3 AFILT4 O Voltage Reference Filter. O Voltage Reference Output 5 mA Drive (Intended for MIC Bias and Power Amp Bias). O Antialiasing Filter Capacitor—ADC Right Channel. O Antialiasing Filter Capacitor—ADC Left Channel. O Antialiasing Filter Capacitor—Mixer ADC Right Channel. O Antialiasing Filter Capacitor—Mixer ADC Left Channel. DVDD1 DVSS1 DVSS2 DVDD2 AVDD1 AVSS1 AVDD2 AVSS2 AVDD3 AVSS3 AVDD4 AVSS4 NC NC I Digital VDD, 3.3 V. I Digital GND. I Digital GND. I Digital VDD, 3.3 V. I Analog VDD, 3.3 V. I Analog GND. I Analog VDD, 3.3 V. I Analog GND. I Analog VDD, 3.3 V. I Analog GND. I Analog VDD, 3.3 V. I Analog GND. No Connect. No Connect. 1 These pins can also be used to select an external clock. See Table 44. 2 These signals are connected to resistors, capacitors, or specific voltages. Rev. A \| Page 11 of 32 11 Page

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