|
|
PDF AD1970 Data sheet ( Hoja de datos )
| Número de pieza | AD1970 | |
| Descripción | Digital BTSC Encoder | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de AD1970 (archivo pdf) en la parte inferior de esta página. Total 20 Páginas | ||
|
No Preview Available !
www.DataSheet4U.com
FEATURES
Complete BTSC encoder
Pilot tone generator
Includes subcarrier modulation
Channel separation: 30 dB
Bandwidth up to 14 kHz
Stereo analog or digital input
Phat-Stereo™ algorithm for stereo image enhancement
Dialog enhancement function for playing wide dynamic
range video sources over built-in TV speakers
Includes L − R dual-band compressor
I2C port for control of modes, effects, and parameters
Analog input performance
74 dB dynamic range
−72 dB THD + N
Digital input performance
87 dB dynamic range
−83 dB THD + N
Integrated op amps for analog inputs and outputs
Single-ended output reduces external part count
Integrated PLL generates all clocks from composite video,
48 kHz sample clock, or high speed master clock
Sync stripper to recover video clock from composite
video signal
Output level control for setting aural carrier deviation
Macrovision™-compliant
Dolby™ RF mode-compatible
48-pin LQFP plastic package
Digital BTSC Encoder
with Integrated ADC and DAC
AD1970
APPLICATIONS
Digital set top box
DVD player
DVD recorder
GENERAL DESCRIPTION
The AD1970 is a complete analog or digital-in, analog-out
BTSC encoder which includes pilot-tone generation and sub-
carrier mixing functions. The stereo ADC provides the means
for digitization of the analog baseband audio signal. A built-in
high performance DAC is provided to output the BTSC base-
band composite signal. The output of the AD1970 can be
connected with minimal external circuitry to the input of a
4.5 MHz aural FM modulator.
In addition to the digital BTSC encoder, the AD1970 includes a
stereo image enhancement function, Phat Stereo, to increase the
sense of spaciousness available from closely spaced TV
loudspeakers. A dialog enhancement algorithm solves the
problem of playing wide dynamic range sources over limited-
performance TV speakers and amplifiers. An I2C port allows
control of the AD1970’s registers and parameters.
The AD1970 utilizes ADI’s patented multibit Σ-Δ architecture to
provide BTSC performance of up to 87 dB dynamic range and a
THD+N of −83 dB.
The AD1970 includes patented BTSC stereo TV technology
licensed from THAT Corporation.
ANALOG L/R
INPUTS
DIGITAL AUDIO
INTERFACE
COMPOSITE
VIDEO
3
I2C I/O
GROUP
4
FUNCTIONAL BLOCK DIAGRAM
ADC
ADC
DECIMATION
FILTER
SYNC
STRIPPER
PLL
AD1970
BTSC
ENCODER
CORE
I2C PORT
CONTROL
REGISTERS
ADC
VOLUME
CONTROL
DAC
BTSC
ENCODED
OUTPUT
ANALOG
BIAS
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved.
1 page  
Table 10. Digital Timing
Parameter
tDMD MCLK Duty Cycle, External 512 fS Mode
tDBL MCLK Low Pulse Width, External 512 fS Mode
tDBH MCLK High Pulse Width, External 512 fS Mode
tDBL MCLK Low Pulse Width, PLL, 256 fS or fS Mode
tDBH MCLK High Pulse Width, PLL, 256 fS or fS Mode
tDLS LRCLK Setup
tDLH LRCLK Hold
tDDS SDATA Setup
tDDH SDATA Hold
tIBC I2C Bus Clock Frequency
tISST I2C Setup Time for Start Condition
tIH I2C Hold Time for Start Condition
tSDS SDA Setup Time
tSDH SDA Hold Time
tSDF SDA Fall Time at 3 mA Sink and 400 pF Load
tSDR SDA Rise Time
tPWS Pulse Width of Spikes Supressed by the Input Filter
tPDRP RESETB Low Pulse Width
AD1970
Min Typ Max Unit
40 50 60 %
15 ns
15 ns
15 ns
15 ns
10 ns
10 ns
10 ns
10 ns
400 kHz
10 ns
30 ns
50 ns
25 ns
25 ns
300 ns
50 ns
15 ns
Rev. 0 | Page 5 of 20
5 Page 
SEPARATION ALIGNMENT
The BTSC encoder outputs are all specified in terms of the
deviation of the FM 4.5 MHz carrier. For the AD1970, a digital
input level of 0 dB (mono signal) should cause a carrier devia-
tion of ±25 kHz without the 75 µs pre-emphasis filter. In
practice, the pre-emphasis filter can be left in for this adjust-
ment, as long as the frequency is low enough to not be affected
by the filter. It is critical to maintain the proper gain relationship
between the BTSC encoder and the 4.5 MHz FM modulator. A
common mistake is to assume that changing the gain between
the BTSC encoder output and the FM modulator input has the
same effect as changing the audio input level going in to the
BTSC encoder. The presence of a complicated 2-band nonlinear
dynamics processor means that the encoder output must be
connected to the decoder input (through the FM modulation/
demodulation process) with a known gain. If this gain is
changed, then the separation significantly suffers.
When measuring the AD1970 on the bench, it is possible to use
a BTSC reference decoder box, so that the FM modulation/
demodulation process can be skipped. These units have a
method of adjusting the input voltage sensitivity to achieve best
separation. The output level of the AD1970 can also be adjusted
over a wide range using either the I2C control port or by
adjusting the values of the components used in the external
analog low-pass filter that is between the BTSC encoder output
and the input to the FM modulator.
PHASE LINEARITY OF THE EXTERNAL ANALOG
FILTER
If the time-alignment of the pilot to the carrier signal is not
close to 0°, a loss of separation can occur. This means that the
external analog low-pass filter should be a linear-phase design
to provide constant group delay over the range from dc to
50 kHz. A Bessel filter is recommended for this application. The
typical applications circuit (see Figure 8) shows a recommended
design for this filter.
INPUT LEVELS
The maximum input level to the AD1970 changes across
frequency. Table 14 shows the maximum allowable input level
for different frequencies. These values are part of the BTSC
specification, not a function of this chip.
AD1970
Table 14. Maximum Input Levels to the BTSC Encoder
across Frequency
Frequency (Hz)
Maximum Input Level (dBFS)
20 to 1000
0
1600
−1
2500
−3
3150
−5
5000
−8
8000
−11
12500
−15
CLOCKING AND PLL
The AD1970’s master clock either can be directly fed to the
MCLK pin or generated by a PLL from a composite video signal
input on the VID_IN pin. If the clock input is on the MCLK pin,
the PLL can synthesize the internal clocks from either a clock at
the digital audio frame sync frequency (fS = 48 kHz) or 256 × fS.
The PLL mode is controlled by Pins PLL_MODE0 and
PLL_MODE1. The settings are shown in Table 15.
Table 15. PLL Modes
PLL_MODE1 PLL_MODE0
00
01
10
11
Setting
Composite video input (on
VID_IN)
256 × fs (on MCLK)
fs (on MCLK)
PLL bypass
CRYSTAL OSCILLATOR
The AD1970 has an on-board crystal oscillator to generate a
clock that can be used by an RF modulator or other application.
For example, a 4 MHz crystal can be connected as shown in the
application circuit (see Figure 8). The AD1970 does not use this
clock itself, so if it is not needed in an application the XIN pin
should be grounded and the XOUT pin left unconnected.
GENERAL PURPOSE INPUT/OUTPUT (GPIO) PINS
Pins GPIO0, GPIO1, GPIO2, and GPIO3 are set to be inputs or
outputs by Bits 19:16 of Control Register 2. All four default to
input state. These pins do not take an input to or send an output
from the main signal flow. When set as an output, the binary
value on the pins is set according to Bits 15:12 of Control
Register 2. These pins can be used to interface with I/O pins on
a microcontroller and allow hardware control via the I2C bus.
POWER-UP SEQUENCE
The AD1970 has a built-in power-up sequence that initializes
the contents of all internal RAMs. During this time, the
parameter RAM is filled with values from its associated boot
ROM. The data memories are also cleared during this time.
The boot sequence lasts for 1024 MCLK cycles and starts on the
rising edge of the RESETB pin. The user should avoid writing to
or reading from the I2C registers during this period of time.
Rev. 0 | Page 11 of 20
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet AD1970.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| AD1970 | Digital BTSC Encoder | Analog Devices |
| AD1974 | ADC | Analog Devices |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |