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AD1938 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD1938
Beschreibung (AD1935 - AD1939) 4 ADC/8 DAC
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 30 Seiten
AD1938 Datasheet, Funktion
www.DataSheet4U.com
Preliminary Technical Data
4 ADC/8 DAC with PLL,
192 kHz, 24 Bit CODEC
AD1935/AD1936/AD1937/AD1938/AD1939
Features
PLL generated (32-192kHz) or direct master clock
Low EMI design
109 dB DAC/ 107dB ADC Dynamic Range and SNR
-94dB THD+N
Single 3.3V Supply
Tolerance for 5V logic inputs
Supports 24-bits and 8 kHz - 192 kHz sample rates
Differential ADC input
Single-ended or Differential DAC output versions
Log volume control with "auto-ramp" function
Hardware and software controllable clickless mute
Software and hardware power-down
Right justified, left justified, I2S and TDM Modes
Master and slave modes up to 16 channel in/out
48-lead LQFP or 64-lead LQFP plastic package
Applications
Automotive audio systems
Home theater systems
Set-top boxes
Digital audio effects processors
GENERAL DESCRIPTION
The AD193X family are high performance, single-chip codecs that
provide 4 ADCs with differential input and 8 DACs with either
single-ended or differential output using ADI’s patented multibit
sigma-delta architecture. An SPI® or I2C® port is included, allowing
a microcontroller to adjust volume and many other parameters.
The AD193X family operates from 3.3V digital and analog supplies.
The AD193X is available in a 48-lead (SE output) or 64-lead
(differential output) LQFP package.
The AD193X is designed for low EMI. This consideration is
apparent in both the system and circuit design architectures. By
using the on-board PLL to derive master clock from L-R clock, the
AD193X eliminates the need for a separate high frequency master
clock. It can also be used with a suppressed bit clock. The D-A and
A-D converters are designed using the latest ADI continuous time
architectures to further minimize EMI. By using 3.3V supplies,
power consumption is minimized, further reducing emissions.
Functional Block Diagram
Digital Audio
Input/Output
Analog
Audio
Inputs
AD193X
Serial Data Port
ADC
SDATAOUT
SDATAIN Digital
Digital
Filter
ADC Filter
&
ADC
CLOCKS
Volume
Control
ADC Timing Management
&
Control
(Clock & PLL)
Precision
Voltage
Reference
Control Port
SPI / I2C
DAC
DAC
DAC
DAC
DAC
DAC
DAC
DAC
Analog
Audio
Outputs
Control Data
Input/Output
Figure 1
Rev. PrI
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703 © 2005 Analog Devices, Inc. All rights reserved.






AD1938 Datasheet, Funktion
AD1935/AD1936/AD1937/AD1938/AD1939
Preliminary Technical Data
ABSOLUTE MAXIMUM RATINGS
Parameter
Min
Analog (AVDD)
–0.3
Digital (DVDD)
–0.3
Input Current (Except Supply Pins)
Analog Input Voltage (Signal Pins) –0.3
Digital Input Voltage (Signal Pins) –0.3
Case Temperature (Operating)
–40
Table 9
Max
+3.6
+3.6
±20
AVDD + 0.3
DVDD + 0.3
+125
Unit
V
V
mA
V
V
°C
Stresses above those listed under the Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress rating
only; functional operation of the device at these or any other
conditions above those indicated in the operational section of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
Package Characteristics
Parameter
Min Typ Max Unit
θJA (Thermal Resistance
50.1 °C/W
[Junction to Ambient]), 48-lead LQFP
θJC (Thermal Resistance
[Junction to Case]), 48-lead LQFP
17 °C/W
θJA (Thermal Resistance
[Junction to Ambient]), 64-lead LQFP
47
°C/W
θJC (Thermal Resistance
[Junction to Case]), 64-lead LQFP
11.1 °C/W
Note: Characteristics are for a 4-layer board
Table 10
Rev. PrI | Page 6 of 30

6 Page









AD1938 pdf, datenblatt
AD1935/AD1936/AD1937/AD1938/AD1939
Preliminary Technical Data
Serial Data Ports—Data Format
The eight DAC channels output or accept a common serial bit clock
and left-right framing clock to clock in the serial data. The four
ADC channels output or accept a common serial bit clock and left-
right framing clock to clock out the data. The clock signals are all
synchronous with the sample rate. In the AUX Modes, set in ADC
Control 1 and DAC Control 0, the DACs use the ADC serial bit
clock and left-right clock as the DAC clock pins are used for the
auxiliary ADC/DAC serial clocks.
The ADC and DAC serial data modes default to I2S. The ports can
also be programmed for left-justified, right-justified and TDM
modes. The word width is 24 bits by default and can be
programmed for 16 or 20 bits. The normal TDM mode can be
daisy-chained with a second AD193X and will support 16 channels
at 48 kHz, 8 channels at 96 kHz or 4 channels at 192 kHz. There is
also a dual-line TDM mode to support 8 channels at 192 kHz.
The special auxiliary modes are provided to allow two external
stereo ADCs and/or two external stereo DACs to be interfaced with
the AD193X to provide up to 8 in/12 out operation or 2 AD193Xs
to be chained for up to 16 in/16 out operation. These modes
provide a glueless interface to a single SHARC serial port, allowing
the DSP to access up to 16 channels of analog I/O. In these modes
many pins are redefined, see table 10. See Figure 18 for details of
these modes.
The following figures show the serial mode formats.
LRCLK
BCLK
SDATA
MSB
LEFT CHANNEL
RIGHT CHANNEL
LSB
MSB
LEFT JUSTIFIED MODE––16 BITS TO 24 BITS PER CHANNEL
LSB
LRCLK
BCLK
SDATA
MSB
LEFT CHANNEL
RIGHT CHANNEL
LSB
MSB
I2S MODE––16 BITS TO 24 BITS PER CHANNEL
LSB
LRCLK
BCLK
SDATA
LEFT CHANNEL
RIGHT CHANNEL
MSB
LSB
MSB
RIGHT JUSTIFIED MODE––SELECT NUMBER OF BITS PER CHANNEL
LSB
LRCLK
BCLK
SDATA
MSB
LSB
MSB
DSP MODE––16 BITS TO 24 BITS PER CHANNEL
1/fS
NOTES
1. DSP MODE DOES NOT IDENTIFY CHANNEL
2. LRCLK NORMALLY OPERATES AT fS EXCEPT FOR DSP MODE WHICH IS 2 × fS
3. BCLK FREQUENCY IS NORMALLY 64 × LRCLK BUT MAY BE OPERATED IN BURST MODE
Figure 13. Stereo Serial Modes
LSB
Rev. PrI | Page 12 of 30

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