AD1935 Datasheet PDF - Analog Devices
| Part Number | AD1935 | |
| Description | (AD1935 - AD1939) 4 ADC/8 DAC | |
| Manufacturers | Analog Devices | |
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Preliminary Technical Data
4 ADC/8 DAC with PLL,
192 kHz, 24 Bit CODEC
AD1935/AD1936/AD1937/AD1938/AD1939
Features
PLL generated (32-192kHz) or direct master clock
Low EMI design
109 dB DAC/ 107dB ADC Dynamic Range and SNR
-94dB THD+N
Single 3.3V Supply
Tolerance for 5V logic inputs
Supports 24-bits and 8 kHz - 192 kHz sample rates
Differential ADC input
Single-ended or Differential DAC output versions
Log volume control with "auto-ramp" function
Hardware and software controllable clickless mute
Software and hardware power-down
Right justified, left justified, I2S and TDM Modes
Master and slave modes up to 16 channel in/out
48-lead LQFP or 64-lead LQFP plastic package
Applications
Automotive audio systems
Home theater systems
Set-top boxes
Digital audio effects processors
GENERAL DESCRIPTION
The AD193X family are high performance, single-chip codecs that
provide 4 ADCs with differential input and 8 DACs with either
single-ended or differential output using ADI’s patented multibit
sigma-delta architecture. An SPI® or I2C® port is included, allowing
a microcontroller to adjust volume and many other parameters.
The AD193X family operates from 3.3V digital and analog supplies.
The AD193X is available in a 48-lead (SE output) or 64-lead
(differential output) LQFP package.
The AD193X is designed for low EMI. This consideration is
apparent in both the system and circuit design architectures. By
using the on-board PLL to derive master clock from L-R clock, the
AD193X eliminates the need for a separate high frequency master
clock. It can also be used with a suppressed bit clock. The D-A and
A-D converters are designed using the latest ADI continuous time
architectures to further minimize EMI. By using 3.3V supplies,
power consumption is minimized, further reducing emissions.
Functional Block Diagram
Digital Audio
Input/Output
Analog
Audio
Inputs
AD193X
Serial Data Port
ADC
SDATAOUT
SDATAIN Digital
Digital
Filter
ADC Filter
&
ADC
CLOCKS
Volume
Control
ADC Timing Management
&
Control
(Clock & PLL)
Precision
Voltage
Reference
Control Port
SPI / I2C
DAC
DAC
DAC
DAC
DAC
DAC
DAC
DAC
Analog
Audio
Outputs
Control Data
Input/Output
Figure 1
Rev. PrI
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703 © 2005 Analog Devices, Inc. All rights reserved.
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Preliminary Technical Data
Parameter
I2C PORT
Start Condition
Stop Condition
Slave Mode
DAC SERIAL PORT
Master Mode
Slave Mode
ADC SERIAL PORT
Master Mode
AUXILIARY INTERFACE
fCCLK
tCDS
tCDH
tCLS
tCLH
tCLH
tCOE
tCOD
tCOH
tCOTS
fSCL
tSCLH
tSCLL
tSCS
tSCH
tDS
tSCR
tSCF
tSDR
tSDF
tSCS
tDBH
tDBL
fDB
tDLS
tDLH
tDLS
tDDS
tDDH
tABH
tABL
fDB
tALS
tALH
tALS
tABDD
tAXDS
tAXDH
tDXDD
tXBH
tXBL
fXB
tDLS
tDLH
AD1935/AD1936/AD1937/AD1938/AD1939
Comments
CCLK Frequency
CDATA Setup
To CCLK Rising
CDATA Hold
From CCLK Rising
CLATCH Setup
To CCLK Rising
CLATCH Hold
From CCLK Falling
CLATCH High
COUT Enable
From CCLK Falling
COUT Delay
COUT Hold
From CCLK Falling
From CCLK Falling
COUT Three-State
SCL Clock
Frequency
From CCLK Falling
SCL High
SCL Low
Setup Time
Relevant for Repeated Start
Condition
Hold Time
After this period the 1st clock is
generated
Data Setup Time
SCL Rise Time
SCL Fall Time
SDA Rise Time
SDA Fall Time
Setup Time
DBCLK High
DBCLK Low
DBCLK Frequency
DLRCLK Setup
To DBCLK Rising
DLRCLK Hold
DLRCLK Skew
From DBCLK Rising
From DBCLK Falling
DSDATA Setup
To DBCLK Rising
DSDATA Hold
From DBCLK Rising
ABCLK High
ABCLK Low
ABCLK Frequency
ALRCLK Setup
To ABCLK Rising
ALRCLK Hold
From ABCLK Rising
ALRCLK Skew
From ABCLK Falling
ASDATA Delay
From ABCLK Falling
AAUXDATA Setup To AUXBCLK Rising
AAUXDATA Hold From AUXBCLK Rising
DAUXDATA Delay From AUXBCLK Falling
AUXBCLK High
AUXBCLK Low
AUXBCLK
Frequency
AUXLRCLK Setup
To AUXBCLK Rising
AUXLRCLK Hold
From AUXBCLK Rising
Table 8
Min Max
20
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
400
0.6
1.3
0.6
0.6
100
300
300
300
300
0.6
TBD
TBD
TBD
TBD
TBD
TBD TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
kHz
µS
µS
µS
µS
ns
ns
ns
ns
ns
µS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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