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PDF ADN2865 Data sheet ( Hoja de datos )
| Número de pieza | ADN2865 | |
| Descripción | Clock and Data Recovery IC | |
| Fabricantes | Analog Devices | |
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Continuous Rate 12.3Mb/s to 2.7Gb/s
Clock and Data Recovery IC w/Loop Timed SERDES
Preliminary Technical Data
ADN2865
FEATURES
Serial data input: 12.3 Mb/s to 2.7 Gb/s
Exceeds ITU-T Jitter Specifications
Integrated Limiting Amp: 6mV sensitivity
Adjustable slice level: ±100 mV
Patented dual-loop clock recovery architecture
Programmable LOS detect and Slice Level
Integrated PRBS Generator and Detector
No reference clock required
Loss of lock indicator
Rate Selectivity without the use of a reference clock
I2C™ interface to access optional features
Single-supply operation: 3.3 V
Low power: 1.0W
8 mm × 8 mm 56-lead LFCSP
APPLICATIONS
Passive Optical Network s
SONET OC-1/3/12/48 and all associated FEC rates
Fibre Channel, 2× Fibre Channel , GbE, HDTV, etc.
WDM transponders
Test equipment
PRODUCT DESCRIPTION
The ADN2865 provides the receiver functions of quantization,
signal level detect, and clock and data recovery for continuous
data rates from 12.3 Mb/s to 2.7 Gb/s. An integrated
deserialiser supports 8 bit parallel transfer to an FPGA or digital
ASIC. The recovered clock can simultaneously serialize data
supplied in an 8 bit parallel format.
The ADN2865 automatically locks to all data rates without the
need for an external reference clock or programming. All
SONET jitter requirements are exceeded, including jitter
transfer, jitter generation, and jitter tolerance. All specifications
are quoted for −40°C to +85°C ambient temperature, unless
otherwise noted.
This device, together with a PIN diode and a TIA preamplifier,
can implement a highly integrated, low cost, low power fiber
optic receiver.
The ADN2865 have many optional features available via an I2C
interface, e.g. the user can read back the data rate that the
ADN2865 is locked on to, or the user can set the device to only
lock to one particular data rate if provisioning of data rates is
required.
FUNCTIONAL BLOCK DIAGRAM
Figure 1 ADN2865 Functional Block Diagram
Rev.PrA
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703 © 2006 Analog Devices, Inc. All rights reserved.
1 page  
Preliminary Technical Data
ADN2865
OUTPUT AND TIMING SPECIFICATIONS
Table 3.
Parameter
CML OUPUT CHARACTERISTICS
Single-Ended Output Swing
Differential Output Swing
Output High Voltage
Output Low Voltage
CML Ouput Timing
Rise Time
Fall Time
LVDS OUPUT CHARACTERISTICS
(RXCLKP/N, RXDATP/N)
Differential Output Swing
Output High Voltage
Output Low Voltage
Output Offset Voltage
Output Impedance
LVDS Ouputs Timing
Rise Time
Fall Time
Setup Time
Hold Time
I2C INTERFACE DC CHARACTERISTICS
Input High Voltage
Input Low Voltage
Input Current
Output Low Voltage
I2C INTERFACE TIMING
SCK Clock Frequency
SCK Pulse Width High
SCK Pulse Width Low
Start Condition Hold Time
Start Condition Setup Time
Data Setup Time
Data Hold Time
SCK/SDA Rise/Fall Time
Stop Condition Setup Time
Bus Free Time between a Stop and a Start
REFCLK CHARACTERISTICS
Input Voltage Range
Minimum Differential Input Drive
Reference Frequency
Required Accuracy
LVTTL DC INPUT CHARACTERISTICS
Input High Voltage
Input Low Voltage
Input High Current
Conditions
VSE (see Figure 75)
VDIFF (see Figure 75)
VOH
VOL
20% to 80%
80% to 20%
VDIFF (see Figure 4)
VOH
VOL
VOS
Differential
20% to 80%
80% to 20%
TS (see Figure 4), OC-48
TH (see Figure 4), OC-48
LVCMOS
VIH
VIL
VIN = 0.1 VCC or VIN = 0.9 VCC
VOL, IOL = 3.0 mA
(See Figure )
tHIGH
tLOW
tHD;STA
tSU;STA
tSU;DAT
tHD;DAT
TR/TF
tSU;STO
tBUF
Optional lock to REFCLK mode
@ REFCLKP or REFCLKN
VIL
VIH
VIH
VIL
IIH, VIN = 2.4 V
Min
300
600
VCC − 0.6
250
925
1125
2.61
-1.70
0.7 VCC
−10.0
600
1300
600
600
100
300
20 + 0.1 Cb1
600
1300
12.3
2.0
Typ Max Unit
350
700
VCC − 0.35
600
1200
VCC
VCC − 0.3
mV
mV
V
V
TBD ps
TBD ps
320
1200
100
115
115
400
1475
1275
220
220
0.3 VCC
+10.0
0.4
400
300
mV
mV
V
V
Ω
ps
ps
ns
ns
V
V
μA
V
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
0V
VCC V
100 mV p-p
200 MHz
100 ppm
V
0.8 V
5 μA
1 Cb = total capacitance of one bus line in pF. If mixed with Hs-mode devices, faster fall-times are allowed (see Table 6).
Rev. PrA | Page 5 of 33
5 Page 
Preliminary Technical Data
Table 5. Pin Function Descriptions
Pin # Mnemonic
Type
Description
1 SDOUT
2 RXDATN1
3 RXDATP1
4 RXDATN0
5 RXDATP0
6 VCC3
7 VCC7
8 SERDATN
9 SERDATP
10 SERCLKN
11 SERCLKP
12 TXDAT7
13 TXDAT6
14 TXDAT5
15 TXDAT4
16 TXCLK
17 TXDAT3
18 TXDAT2
19 TXDAT1
20 TXDAT0
21 VREG
22 CF1
23 VEE2
24 VCC2
25 VEE4
26 VCC4
27 REFN
28 REFP
29 THRADJ
30 LOL
31 VEE1
32 SLICEN
33 SLICEP
34 NIN
35 PIN
36 VREF
37 VCC1
38 SCK
39 VCC6
40 SDA
41 RXCLKN
42 RXCLKP
43 RXDATN7
44 RXDATP7
45 VCC5
46 RXDATN6
47 RXDATP6
48 RXDATN5
49 RXDATP5
50 VCC5
51 RXDATN4
52 RXDATP4
53 RXDATN3
54 RXDATP3
55 RXDATN2
56 RXDATP2
DO
DO
DO
DO
DO
PWR
PWR
DO
DO
DO
DO
DI
DI
DI
DI
DI
DI
DI
DI
DI
AO
AO
PWR
PWR
PWR
PWR
DI
DI
AO
DO
PWR
AI
AI
AI
AI
AO
PWR
DI
PWR
DI
DO
DO
DO
DO
PWR
DO
DO
DO
DO
PWR
DO
DO
DO
DO
DO
DO
Active high, Loss of signal indicator. (LVTTL)
Differential receive data output. (LVDS)
Differential receive data output. (LVDS)
Differential receive data output. Last bit received. (LVDS)
Differential receive data output. Last bit received. (LVDS)
Power for CDR & Serialiser
Power for CML drivers
Differential serialized data output to LDD. (CML)
Differential serialized data output to LDD. (CML)
Differential clock for serialized Tx data. (CML)
Differential clock for serialized Tx data. (CML)
Transmit data input. First bit sent. (LVTTL)
Transmit data input. (LVTTL)
Transmit data input. (LVTTL)
Transmit data input. (LVTTL)
Qualifying clock for transmit data input. (LVTTL)
Transmit data input. (LVTTL)
Transmit data input. (LVTTL)
Transmit data input. (LVTTL)
Transmit data input. Last bit sent. (LVTTL)
Decoupling node for VCO power.
PLL loop filter capacitor.
Ground for VCO / PLL / Gm
Power for VCO / PLL / Gm
Ground for FLL
Power for FLL
Reference clock input. (LVDS/LVTTL)
Reference clock input. (LVDS/LVTTL)
LOS Threshold Setting Resistor.
Active high, Loss-of-Lock Indicator. (LVTTL)
Ground for Limamp / LOS
Differential Slice Level Adjust Input.
Differential Slice Level Adjust Input.
Differential serial input to Limiting Amp. (CML)
Differential serial input to Limiting Amp. (CML)
Decoupling node for internal voltage reference.
Power for Limamp / LOS
I2C Serial Clock Input.
Power for Deserialiser, LVDS pre-drivers
I2C Serial Data Input.
Qualifying clock for Rx Data Outputs. (LVDS)
Qualifying clock for Rx Data Outputs. (LVDS)
Differential receive data output. Last bit received. (LVDS)
Differential receive data output. Last bit received. (LVDS)
Power for LVDS drivers
Differential receive data output. (LVDS)
Differential receive data output. (LVDS)
Differential receive data output. (LVDS)
Differential receive data output. (LVDS)
Power for LVDS Drivers
Differential receive data output. (LVDS)
Differential receive data output. (LVDS)
Differential receive data output. (LVDS)
Differential receive data output. (LVDS)
Differential receive data output. (LVDS)
Differential receive data output. (LVDS)
1Type: P = power, AI = analog input, AO = analog output, DI = digital input, DO = digital output.
Rev. PrA | Page 11 of 33
ADN2865
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ADN2865.PDF ] | |
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