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ADN2817 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer ADN2817
Beschreibung (ADN2817 / ADN2818) Clock and Data Recovery IC
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 30 Seiten
ADN2817 Datasheet, Funktion
www.DataSheet4U.com
Preliminary Technical Data
Continuous Rate 12.3Mb/s to 2.7Gb/s
Clock and Data Recovery ICs
ADN2817/ADN2818
FEATURES
Serial data input: 12.3 Mb/s to 2.7 Gb/s
Exceeds ITU-T Jitter Specifications
Integrated Limiting Amp: 6mV sensitivity (ADN2817 only)
Adjustable slice level: ±100 mV (ADN2817 only)
Patented dual-loop clock recovery architecture
Programmable LOS detect (ADN2817 only)
Slice level and sample phase adjustments (ADN2817 only)
Integrated PRBS Generator and Detector
No reference clock required
Loss of lock indicator
Supports Double Data Rate
Relative Bit Error Rate Monitor
Rate Selectivity without the use of a reference clock
I2C™ interface to access optional features
Single-supply operation: 3.3 V
Low power: 650/600 mW (ADN2817/ADN2818)
5 mm × 5 mm 32-lead LFCSP
APPLICATIONS
SONET OC-1/3/12/48 and all associated FEC rates
Fibre Channel, 2× Fibre Channel , GbE, HDTV, etc.
WDM transponders
Regenerators/repeaters
Test equipment
FUNCTIONAL
BLOCK DIAGRAM
REFCLKP/N
(optional)
LOL
PRODUCT DESCRIPTION
The ADN2817/ADN2818 provides the receiver functions of
quantization, signal level detect, and clock and data recovery for
continuous data rates from 12.3 Mb/s to 2.7 Gb/s. The
ADN2817/ADN2818 automatically locks to all data rates
without the need for an external reference clock or
programming. All SONET jitter requirements are exceeded,
including jitter transfer, jitter generation, and jitter tolerance.
All specifications are quoted for −40°C to +85°C ambient
temperature, unless otherwise noted.
This device, together with a PIN diode and a TIA preamplifier,
can implement a highly integrated, low cost, low power fiber
optic receiver.
The ADN2817/ADN2818 have many optional features available
via an I2C interface, e.g. the user can read back the data rate that
the ADN2817/ADN2818 is locked on to, or the user can set the
device to only lock to one particular data rate if provisioning of
data rates is required.
The ADN2817/ADN2818 is available in a compact 5 mm × 5
mm 32-lead chip scale package.
CF1 CF2 VCC VEE
SLICEP/N
Slice Adjust
(ADN2817
only)
PIN
NIN
Phase
Shifter
VREF
LOS Detect
(ADN2817
only)
Data
Re-Timing
Freq/
Lock
Det
Phase
Det.
Loop
Filter
Loop
Filter
THRADJ SDOUT DATAOUTP/N
CLKOUTP/N
Σ VCO
I2C
Registers
SCK SDA
Figure 1 ADN2817/ADN2818 Functional Block Diagram
Rev.PrA
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703 © 2006 Analog Devices, Inc. All rights reserved.






ADN2817 Datasheet, Funktion
ADN2817/ADN2818
Preliminary Technical Data
BIT ERROR RATE MONITOR (BERMON) SPECIFICATIONS
TA = TMIN to TMAX, VCC = VMIN to VMAX, VEE = 0 V, CF = 0.47 uF, SLICEP = SLICEN = VEE, Input Data Pattern: PRBS 223 − 1,
unless otherwise noted.
Table 4.
Parameter
BERMON Primary Mode
BER Accuracy
Numbits
Measurement Time
Sample Phase Adjust Resolution
BER Range
Power Increase
BERMON Secondary Mode
BER Accuracy
BER Accuracy
Numbits
Measurement Time
Sample Phase Adjust Resolution
VBER
Power Increase
Conditions
I2C Controlled Eye Profiling
Input BER Range 1e-3 to 1e-12, Input
DJ<0.4UI, DJ Ceiling>1e-2.
Asymmetry <0.1UI. Requires external
data processing algorithms to
implement Q factor extrapolation.
Number of data bits to collect
pseudo-errors. User programmable in
increment factors of 23 over the range
218 to 239.
Min
218
BER On
BER Standby
Analog Voltage Output
Input BER Range 1e-3 to 1e-9, Input
DJ=0 UI, DJ Ceiling>1e-2. Asymmetry
=0 UI. BER is read as a voltage on pin
VBER, when Automode = 0.
Input BER Range 1e-3 to 1e-9, Input
DJ=0.2 UI, DJ Ceiling>1e-2.
Asymmetry =0 UI. BER is read as a
voltage on pin VBER, when Automode
= 0.
Number of data bits to collect
pseudo-errors.
2.5Gb/s
1Gb/s
155Mb/s
10Mb/s
see Figure xx
BER Automode
0.1
Typ Max
+/-1
239
Numbits/Datarate
6
177
88
5e-2
+/-1
+1/-2
227
0.054
0.134
0.865
1.34
6
177
0.9
Unit
Decades
UI
s
degrees
BER
mW
mW
Decades
Decades
UI
s
s
s
s
degrees
V
mW
Rev. PrA | Page 6 of 35

6 Page









ADN2817 pdf, datenblatt
ADN2817/ADN2818
Preliminary Technical Data
Table 6. Internal Register Map1
Reg Name R/W ADDRESS
D7
D6
FREQ0
R
0x0
MSB
FREQ1
R
0x1
MSB
FREQ2
R
0x2
0 MSB
RATE
R
0x3 COARSE_RD[8] MSB
MISC R 0x4
x
x
CTRLA W
0x8 FREF Range
D5 D4
D3
D2
D1
D0
LSB
LSB
LSB
Coarse Data Rate Readback
COARSE_RD[1]
LOS status Static LOL
LOL status
datarate meas
complete
x
COARSE_RD[0]
LSB
Data Rate/DIV FREF Ratio
Measure Data
Lock to
Rate
Reference
CTRLA_RD R
0x5
readback CTRLA
CTRLB
W
0x9
Config LOL
Reset
MISC[4]
System
Reset
0
Reset
MISC[2]
0
0
0
CTRLB_RD R
0x6
readback CTRLB
CTRLC
W
0x11
0
0
Set Signal
Degrade
Threshold
Enable
Signal
Degrade
LOS forces
acquisition
Config LOS Squelch Mode
Boost Output
CTRLD
W
0x22
CDR
Bypass
Disable
DATA
Buffer
Disable
CLK Buffer
Initiate
PRBS
Sequence
PRBS Mode[2..0]
FDDI_MODE W
0x0D
FDDI Mode
Enable
Subharmonic Ratio
00
SEL_MODE W
0x34
0
0
Acq Mode
Cont Rate /
Single Rate
Datarate
Range
CLK Holdover CLK Holdover
Mode 2A
Mode 2B
0
HI_CODE W
0x35 HI_CODE[8]
HI_CODE[1]
LO_CODE W
0x36 LO_CODE[8]
LO_CODE[1]
CODE_LSB W
0x39
0
00
0
0
0 HI_CODE[0] LO_CODE[0]
BERCTLA W
0x1E
BER Timer
Phase
Polarity
BER Start
Pulse
Error Count Byte Select, e.g. 011=Byte 3 of 5
BERCTLB W
0x1F
0
0
Enable BER Stdby Clock XOR
BER
Mode
Input
BER Mode
BERSTS R
0x20
x
xx
x
x
x
x
BER Meas
Status
BER_RES R
0x21
BER_RES[7..0], BER Measurement Result
BER_DAC R
0x24
BER_DAC[7..0], Output of BER DAC
PHASE W
0x37
PHASE[7..0], 2's Complement Sample Phase Offset Adjustment
1 All writeable registers default to 0x00.
Table 7. Miscellaneous Register, MISC
LOS Status
D7 D6 D5
x x 0 = No loss of signal
1 = Loss of signal
Static LOL
D4
0 = Waiting for next LOL
1 = Static LOL until reset
LOL Status
D3
0 = Locked
1 = Acquiring
Datarate Measurement
Complete
D2
0 = Measuring datarate
1 = Measurement complete
D1
x
Coarse Rate
Readback LSB
D0
COARSE_RD[0]
Table 8. Control Register, CTRLA1
FREF Range
Datarate/Div_FREF Ratio
D7 D6
D5 D4 D3 D2
0 0 12.3 MHz to 25 MHz 0 0 0 0 1
0 1 25 MHz to 50 MHz
00012
1 0 50 MHz to 100 MHz 0 0 1 0 4
1 1 100 MHz to 200 MHz
n 2n
1 0 0 0 256
Measure Datarate
D1
Set to 1 to measure datarate
Lock to Reference
D0
0 = Lock to input data
1 = Lock to reference clock
1 Where DIV_FREF is the divided down reference referred to the 12.3 MHz to 25 MHz band (see the Reference Clock (Optional) section).
Rev. PrA | Page 12 of 35

12 Page





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