PDF ADN2813 Data sheet ( Hoja de datos )

Número de pieza	ADN2813
Descripción	Clock and Data Recovery IC
Fabricantes	Analog Devices
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1. ADN2813 pinout Hay una vista previa y un enlace de descarga de ADN2813 (archivo pdf) en la parte inferior de esta página. Total 28 Páginas
No Preview Available ! www.DataSheet4U.com Continuous Rate 10 Mb/s to 1.25 Gb/s Clock and Data Recovery IC with Integrated Limiting Amp ADN2813 FEATURES Serial data input: 10 Mb/s to 1.25 Gb/s Exceeds SONET requirements for jitter transfer/ generation/tolerance Quantizer sensitivity: 3.3 mV typ Adjustable slice level: ±95 mV Patented clock recovery architecture Loss-of-signal (LOS) detect range: 2.3 mV to 19 mV Independent slice level adjust and LOS detector No reference clock required Loss-of-lock indicator I2C® interface to access optional features Single-supply operation: 3.3 V Low power: 450 mW typ 5 mm × 5 mm 32-lead LFCSP, Pb free APPLICATIONS SONET OC-1/-3/-12 and all associated FEC rates Fibre Channel, GbE, HDTVs WDM transponders Regenerators/repeaters Test equipment Broadband cross-connects and routers GENERAL DESCRIPTION The ADN2813 provides the receiver functions of quantization, signal level detect, and clock and data recovery for continuous data rates from 10 Mb/s to 1.25 Gb/s. The ADN2813 automati- cally locks to all data rates without the need for an external reference clock or programming. All SONET jitter requirements are met, including jitter transfer, jitter generation, and jitter tolerance. All specifications are quoted for −40°C to +85°C ambient temperature, unless otherwise noted. This device, together with a PIN diode and a TIA preamplifier, can implement a highly integrated, low cost, low power fiber optic receiver. The receiver front-end, loss-of-signal (LOS) detector circuit indicates when the input signal level has fallen below a user- adjustable threshold. The LOS detect circuit has hysteresis to prevent chatter at the output. The ADN2813 is available in a compact 5 mm × 5 mm, 32-lead LFCSP. FUNCTIONAL BLOCK DIAGRAM REFCLKP/N (OPTIONAL) LOL CF1 CF2 VCC VEE SLICEP/N PIN NIN 2 QUANTIZER FREQUENCY DETECT LOOP FILTER PHASE SHIFTER PHASE DETECT LOOP FILTER VCO VREF LOS DETECT DATA RE-TIMING 2 2 THRADJ LOS DATAOUTP/N CLKOUTP/N ADN2813 Figure 1. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved. 1 page ADN2813 OUTPUT AND TIMING SPECIFICATIONS Table 3. Parameter LVDS OUTPUT CHARACTERISTICS (CLKOUTP/CLKOUTN, DATAOUTP/DATAOUTN) Output Voltage High Output Voltage Low Differential Output Swing Differential Output Swing Output Offset Voltage Output Impedance LVDS Outputs Timing Rise Time Fall Time Setup Time Hold Time I2C INTERFACE DC CHARACTERISTICS Input High Voltage Input Low Voltage Input Current Output Low Voltage I2C INTERFACE TIMING SCK Clock Frequency SCK Pulse Width High SCK Pulse Width Low Start Condition Hold Time Start Condition Setup Time Data Setup Time Data Hold Time SCK/SDA Rise/Fall Time Stop Condition Setup Time Bus Free Time Between a Stop and a Start REFCLK CHARACTERISTICS Input Voltage Range Minimum Differential Input Drive Reference Frequency Required Accuracy LVTTL DC INPUT CHARACTERISTICS Input High Voltage Input Low Voltage Input High Current Input Low Current LVTTL DC OUTPUT CHARACTERISTICS Output High Voltage Output Low Voltage Conditions VOH (see Figure 3), 655 Mb/s VOL (see Figure 3), 655 Mb/s VOD (see Figure 3), 655 Mb/s VOD (see Figure 3), 1.25 Gb/s VOS (see Figure 3) Differential GbE 20% to 80% 80% to 20% TS (see Figure 2), GbE TH (see Figure 2), GbE LVCMOS VIH VIL VIN = 0.1 VCC or VIN = 0.9 VCC VOL, IOL = 3.0 mA See Figure 11 tHIGH tLOW tHD;STA tSU;STA tSU;DAT tHD;DAT TR/TF tSU;STO tBUF Optional lock to REFCLK mode @ REFCLKP or REFCLKN VIL VIH VIH VIL IIH, VIN = 2.4 V IIL, VIN = 0.4 V VOH, IOH = −2.0 mA VOL, IOL = 2.0 mA 1 Cb = total capacitance of one bus line in pF. If mixed with Hs mode devices, faster fall times are allowed. Min Typ Max Unit 925 250 240 1125 1475 320 300 1200 100 400 400 1275 mV mV mV mV Ω 115 220 ps 115 220 ps 360 400 440 ps 360 400 440 ps 0.7 VCC −10.0 0.3 VCC +10.0 0.4 V V μA V 600 1300 600 600 100 300 20 + 0.1 Cb1 600 1300 400 kHz ns ns ns ns ns ns 300 ns ns ns 0V VCC V 100 mV p-p 10 160 MHz 100 ppm 2.0 V 0.8 V 5 μA −5 μA 2.4 V 0.4 V Rev. 0 \| Page 5 of 28 5 Page ADN2813 Table 6. Internal Register Map1 Reg. Name R/W Address D7 D6 D5 FREQ0 R 0x0 MSB FREQ1 R 0x1 MSB FREQ2 R 0x2 0 MSB RATE R 0x3 COARSE_RD[8] MSB MISC R 0x4 x x LOS Status CTRLA W CTRLB W CTRLC W 0x8 0x9 0x11 FREF Range Config. Reset LOL MISC[4] 00 System Reset 0 D4 D3 D2 Coarse Data Rate Readback Static LOL LOL Status Data Rate Measure Complete Data Rate/DIV_FREF Ratio 0 Reset MISC[2] 0 00 Config. LOS 1 All writeable registers default to 0x00. D1 D0 LSB LSB LSB COARSE_RD[1] x COARSE_RD[0] LSB Measure Data Rate 0 SQUELCH Mode Lock to Reference 0 Output Boost Table 7. Miscellaneous Register, MISC LOS Status D7 D6 D5 x x 0 = No loss of signal 1 = Loss of signal Static LOL D4 0 = Waiting for next LOL 1 = Static LOL until reset LOL Status D3 0 = Locked 1 = Acquiring Data Rate Measurement Complete D2 0 = Measuring data rate 1 = Measurement complete Coarse Rate Readback LSB D1 D0 x COARSE_RD[0] Table 8. Control Register, CTRLA1 FREF Range Data Rate/Div_FREF Ratio D7 D6 D5 D4 D3 D2 0 0 10 MHz to 20 MHz 00001 0 1 20 MHz to 40 MHz 00012 1 0 40 MHz to 80 MHz 00104 1 1 80 MHz to 160 MHz n 2n 1 0 0 0 256 Measure Data Rate D1 Set to 1 to measure data rate Lock to Reference D0 0 = Lock to input data 1 = Lock to reference clock 1 Where DIV_FREF is the divided down reference referred to the 10 MHz to 20 MHz band (see the Reference Clock (Optional) section). Table 9. Control Register, CTRLB Config LOL Reset MISC[4] System Reset Reset MISC[2] D7 D6 D5 D4 D3 D2 D1 D0 0 = LOL pin normal operation 1 = LOL pin is static LOL Write a 1 followed by Write a 1 followed by 0 Set Write a 1 followed by 0 Set Set Set 0 to reset MISC[4] to reset ADN2813 to 0 to reset MISC[2] to 0 to 0 to 0 Table 10. Control Register, CTRLC D7 D6 D5 D4 Set to 0 Set to 0 Set to 0 Set to 0 D3 Set to 0 Config. LOS D2 0 = Active high LOS 1 = Active low LOS SQUELCH Mode D1 0 = SQUELCH CLK and DATA 1 = SQUELCH CLK or DATA Output Boost D0 0 = Default output swing 1 = Boost output swing Rev. 0 \| Page 11 of 28 11 Page

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