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PDF ADN2806 Data sheet ( Hoja de datos )
| Número de pieza | ADN2806 | |
| Descripción | Clock and Data Recovery IC | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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FEATURES
Exceeds SONET requirements for jitter transfer/
generation/tolerance
Patented clock recovery architecture
No reference clock required
Loss-of-lock indicator
I2C® interface to access optional features
Single-supply operation: 3.3 V
Low power: 359 mW typical
5 mm × 5 mm, 32-lead LFCSP, Pb free
APPLICATIONS
BPON ONT
SONET OC-12
WDM transponders
Regenerators/repeaters
Test equipment
Broadband cross-connects and routers
622 Mbps Clock and Data Recovery IC
ADN2806
GENERAL DESCRIPTION
The ADN2806 provides the receiver functions for clock and
data recovery, and data retiming for 622 Mbps NRZ data. The
ADN2806 automatically locks to 622 Mbps data without the
need for an external reference clock or programming. In the
absence of input data, the output clock drifts no more than
±5%. All SONET jitter requirements are met, including jitter
transfer, jitter generation, and jitter tolerance. All specifications
are quoted for −40°C to +85°C ambient temperature, unless
otherwise noted.
This device, together with a PIN diode, TIA preamplifier, and a
lim amp can implement a highly integrated, low cost, low power
fiber optic receiver.
The ADN2806 is available in a compact 5 mm × 5 mm,
32-lead LFCSP.
FUNCTIONAL BLOCK DIAGRAM
REFCLKP/REFCLKN
(OPTIONAL)
LOL
CF1
CF2 VCC VEE
PIN
NIN
VREF
FREQUENCY
DETECT
LOOP
FILTER
BUFFER
PHASE
SHIFTER
PHASE
DETECT
LOOP
FILTER
VCO
DATA
RE-TIMING
2
2
DATAOUTP/
DATAOUTN
CLKOUTP/
CLKOUTN
Figure 1.
ADN2806
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.
1 page  
ABSOLUTE MAXIMUM RATINGS
TA = TMIN to TMAX, VCC = VMIN to VMAX, VEE = 0 V, CF =
0.47 μF, unless otherwise noted.
Table 4.
Parameter
Supply Voltage (VCC)
Minimum Input Voltage (All Inputs)
Maximum Input Voltage (All Inputs)
Maximum Junction Temperature
Storage Temperature Range
Rating
4.2 V
VEE − 0.4 V
VCC + 0.4 V
125°C
−65°C to +150°C
ADN2806
Stress above those listed under Absolute Maximum Ratings may
cause permanent damage to the device. This is a stress rating
only; functional operation of the device at these or any other
conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL CHARACTERISTICS
Thermal Resistance
32-lead LFCSP, 4-layer board with exposed paddle soldered to
VEE, θJA = 28°C/W.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. 0 | Page 5 of 20
5 Page 
THEORY OF OPERATION
The ADN2806 is a delay- and phase-locked loop circuit for
clock recovery and data retiming from an NRZ encoded data
stream. The phase of the input data signal is tracked by two
separate feedback loops, which share a common control voltage.
A high speed delay-locked loop path uses a voltage controlled
phase shifter to track the high frequency components of input
jitter. A separate phase control loop, composed of the VCO,
tracks the low frequency components of input jitter. The initial
frequency of the VCO is set by yet a third loop that compares
the VCO frequency with the input data frequency and sets the
coarse tuning voltage. The jitter tracking phase-locked loop
controls the VCO by the fine-tuning control.
The delay and phase loops together track the phase of the input
data signal. For example, when the clock lags the input data, the
phase detector drives the VCO to a higher frequency and
increases the delay through the phase shifter; both of these
actions serve to reduce the phase error between the clock and
the data. The faster clock picks up phase, whereas the delayed
data loses phase. Because the loop filter is an integrator, the
static phase error is driven to 0°.
Another view of the circuit is that the phase shifter implements
the zero required for frequency compensation of a second-order
phase-locked loop, and this zero is placed in the feedback path;
therefore, it does not appear in the closed-loop transfer
function. Jitter peaking in a conventional second-order phase-
locked loop is caused by the presence of this zero in the closed-
loop transfer function. Because this circuit has no zero in the
closed-loop transfer, jitter peaking is minimized.
The delay and phase loops together simultaneously provide
wideband jitter accommodation and narrow-band jitter
filtering. The linearized block diagram in Figure 13 shows that
the jitter transfer function, Z(s)/X(s), provides excellent second-
order low-pass filtering. Note that the jitter transfer has no zero,
unlike an ordinary second-order phase-locked loop. This means
that the main PLL loop has virtually no jitter peaking (see
Figure 14), making this circuit ideal for signal regenerator
applications, where jitter peaking in a cascade of regenerators
can contribute to hazardous jitter accumulation.
The error transfer, e(s)/X(s), has the same high-pass form as an
ordinary phase-locked loop. This transfer function can be
optimized to accommodate a significant amount of wideband
jitter, because the jitter transfer function, Z(s)/X(s), provides the
narrow-band jitter filtering.
ADN2806
INPUT X(s)
DATA
psh
e(s)
d/sc
o/s
Z(s)
RECOVERED
CLOCK
1/n
d = PHASE DETECTOR GAIN
o = VCO GAIN
c = LOOP INTEGRATOR
psh = PHASE SHIFTER GAIN
n = DIVIDE RATIO
JITTER TRANSFER FUNCTION
Z(s)
X(s)
=
s2
cn
do
+
1
sn
psh
o
+
1
TRACKING ERROR TRANSFER FUNCTION
e(s)
X(s)
=
s2 +
s2
s
d
psh
c
+
do
cn
Figure 13. PLL/DLL Architecture
JITTER PEAKING
IN ORDINARY PLL
ADN2806
Z(s)
X(s)
o
n psh
d psh
c
FREQUENCY (kHz)
Figure 14. Jitter Response vs. Conventional PLL
The delay and phase loops contribute to overall jitter accom-
modation. At low frequencies of input jitter on the data signal,
the integrator in the loop filter provides high gain to track large
jitter amplitudes with small phase error. In this case, the VCO is
frequency modulated, and jitter is tracked as in an ordinary
phase-locked loop. The amount of low frequency jitter that can
be tracked is a function of the VCO tuning range. A wider
tuning range gives larger accommodation of low frequency
jitter. The internal loop control voltage remains small for small
phase errors; therefore, the phase shifter remains close to the
center of its range and thus contributes little to the low
frequency jitter accommodation.
Rev. 0 | Page 11 of 20
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet ADN2806.PDF ] | |
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