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ADM1170 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer ADM1170
Beschreibung Hot Swap Controller
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 17 Seiten
ADM1170 Datasheet, Funktion
Data Sheet
1.6 V to 16.5 V Hot Swap Controller
with Soft Start
ADM1170
FEATURES
Controls supply rails from 1.6 V to 16.5 V
Supply voltage range from 2.7 V to 16.5 V
Allows protected board removal and insertion to a live
backplane
External sense resistor provides adjustable analog current
limit with circuit breaker
Soft start controls inrush current profile
Peak fault current limited with fast response
Charge pumped gate drive for external N-FET switch
Automatic retry or latch-off during current fault
Undervoltage lockout
8-lead, TSOT package
APPLICATIONS
Hot swap board insertion: line cards, raid systems
Industrial high-side switches/circuit breakers
Electronic circuit breakers
GENERAL DESCRIPTION
The ADM1170 is a hot swap controller that safely enables a
printed circuit board to be removed and inserted to a live
backplane. This is achieved using an external N-channel power
MOSFET with a current control loop that monitors the load
current through a sense resistor. An internal charge pump is
used to enhance the gate of the N-channel FET. When an
overcurrent condition is detected, the gate voltage of the FET is
reduced to limit the current flowing through the sense resistor.
The ADM1170 operates with a supply voltage ranging from
2.7 V to 16.5 V. By using independent SENSE pins from VCC,
the ADM1170 allows for the hot swap of supplies ranging down
to 1.6 V. During an overcurrent condition, the TIMER pin
capacitor determines the amount of time the FET remains at
a current limiting mode of operation until it is shut down. The
ON (ON-CLR) pin is the enable input for the device and can be
used to monitor the input supply voltage. The ADM1170 also
features soft start to provide the user with a capacitor program-
mable ramping reference to the internal current sense comparator.
This provides a linearly increasing current limit at startup at a
rate set by CSS. This helps to reduce and limit large inrush
currents.
This device is available in two options: the ADM1170-1 with
automatic retry for overcurrent fault and the ADM1170-2 with
latch-off for an overcurrent fault. Toggling the ON (ON-CLR)
pin resets a latched fault. The ADM1170 is packaged in an
8-lead TSOT.
VIN = 1.8V
VIN = 3.3VAUX
GND
FUNCTIONAL BLOCK DIAGRAM
LONG
RSENSE
LONG
SHORT RON1
RON2
LONG
SENSE+ SENSE–
VCC
GATE
ADM1170-1
ON
SS
CSS
TIMER
GND
CTIMER
Figure 1.
Q1 VOUT = 1.8V
CLOAD
GND
Rev. A
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ADM1170 Datasheet, Funktion
Data Sheet
ADM1170
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
ADM1170-1AUJ
TIMER 1
8 VCC
GND 2 TOP VIEW 7 SENSE+
SS 3 (Not to Scale) 6 SENSE–
ON 4
5 GATE
Figure 2. Pin Configuration, 1AUJ Model
ADM1170-2AUJ
TIMER 1
8 VCC
GND 2 TOP VIEW 7 SENSE+
SS 3 (Not to Scale) 6 SENSE–
ON-CLR 4
5 GATE
Figure 3. Pin Configuration, 2AUJ Model
Table 4. Pin Function Descriptions
Pin No. Mnemonic
Description
1 TIMER
Timer Input Pin. The initial and circuit breaker timing cycles are set by this external capacitor. The initial timing
delay is 272.9 ms/μF, and 21.7 ms/µF for a circuit breaker delay. When the TIMER pin is pulled beyond the
upper threshold, the GATE turns off.
2 GND
Chip Ground Pin.
3 SS
Soft Start Pin. An external capacitor between the SS pin and GND sets the ramp rate of the current limit
reference.
4
ON (ON-CLR)
Input Pin. The ON (ON-CLR) pin is an input to a comparator that has a low-to-high threshold of 1.3 V with
80 mV hysteresis and a glitch filter. The ADM1170 is reset when the ON (ON-CLR) pin is low. When the ON
(ON-CLR) pin is high, the ADM1170 is enabled. A rising edge on this pin has the added function of clearing a
fault and restarting the device on the latched off model, the ADM1170-2.
5 GATE
Gate Output Pin. An internal charge pump provides a 12 µA pull-up current to drive the gate of an N-channel
MOSFET. In an overcurrent condition, the ADM1170 controls the external FET to maintain a constant load
current.
6, 7 SENSE−, SENSE+ Current Limit Sense Input Pins. The current limit is set via a sense resistor between the SENSE+ and SENSE−
pins. In an overcurrent condition, the gate of the FET is controlled to maintain the SENSE voltage at 50 mV.
When this limit is reached, the TIMER circuit breaker mode is activated. The circuit breaker limit can be
disabled by connecting the SENSE+ and SENSE− pins together.
8 VCC
Positive Supply Input Pin. The ADM1170 operates between 2.7 V to 16.5 V. An undervoltage lockout (UVLO)
circuit with a glitch filter resets the ADM1170 when the supply voltage drops below the specified UVLO limit.
Rev. A | Page 5 of 16

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ADM1170 pdf, datenblatt
Data Sheet
ADM1170
THEORY OF OPERATION
Many systems require the insertion or removal of circuit boards
to live backplanes. During this event, the supply bypass and hold-
up capacitors can require substantial transient currents from the
backplane power supply as they charge. These currents can
cause permanent damage to connector pins or undesirable glitches
and resets to the system.
The ADM1170 is intended to control the powering of a system
(on and off) in a controlled manner, allowing the board to be
removed from, or inserted into, a live backplane by protecting it
from excess currents. The ADM1170 can reside either on the
backplane or on the removable board.
OVERVIEW
The ADM1170 operates over a supply range of 2.7 V to 16.5 V.
As the supply voltage is coming up, an undervoltage lockout
circuit checks if sufficient supply voltage is present for proper
operation. During this period, the FET is held off by the GATE
pin being held to GND. When the supply voltage reaches a level
above UVLO and the ON (ON-CLR) pin is high, an initial timing
cycle ensures that the board is fully inserted in the backplane
before turning on the FET. The TIMER pin capacitor sets the
periods for all of the TIMER pin functions. After the initial
timing cycle, the ADM1170 monitors the inrush current
through an external sense resistor. Overcurrent conditions are
actively limited to 50 mV/RSENSE for the circuit breaker timer
limit. The ADM1170-1 automatically retries after a current limit
fault and the ADM1170-2 latches off. The retry duty cycle on
the ADM1170-1 timer function is limited to 3.8% for FET
cooling.
UVLO
If the VCC supply is too low for normal operation, an under-
voltage lockout circuit holds the ADM1170 in reset. The GATE
pin is held to GND during this period. When the supply reaches
this UVLO voltage, the ADM1170 starts when the ON (ON-CLR)
pin condition is satisfied.
ON (ON-CLR) PIN
The ON (ON-CLR) pin is the enable pin. It is connected to a
comparator that has a low-to-high threshold of 1.3 V with 80 mV
hysteresis and a glitch filter. The ADM1170 is reset when the
ON (ON-CLR) pin is low. When the ON (ON-CLR) pin is high,
the ADM1170 is enabled. A rising edge on this pin has the
added function of clearing a fault and restarting the device on
the latched off model, the ADM1170-2. A low input on the ON
(ON-CLR) pin turns off the external FET by pulling the GATE
pin to ground and resets the timer. An external resistor divider at
the ON (ON-CLR) pin can be used to program an undervoltage
lockout value higher than the internal UVLO circuit. There is a
glitch filter delay of approximately 3 μs on rising allowing the
addition of an RC filter at the ON (ON-CLR) pin to increase the
delay time at card insertion. If using a short pin system to
enable the device, a pull-down resistor should be used to hold
the device prior to insertion.
GATE
Gate drive for the external N-channel MOSFET is achieved
using an internal charge pump. The gate driver consists of a
12 μA pull-up from the internal charge pump. There are various
pull-down devices on this pin. At a hotswap condition the board
is hot inserted to the supply bus. During this event, it is possible
for the external FET GATE capacitance to be charged up by the
sudden presence of the supply voltage. This can cause
uncontrolled inrush currents. An internal strong pull-down
circuit holds GATE low while in UVLO. This reduces current
surges at insertion. After the initial timing cycle, the GATE is
then pulled high. During an overcurrent condition, the
ADM1170 servos the GATE pin in an attempt to maintain a
constant current to the load until the circuit breaker timeout
completes. In the event of a timeout, the GATE pin abruptly
shuts down using the 4 mA pull-down device. Care must be
taken not to load the GATE pin resistively because this reduces
the gate drive capability.
CURRENT LIMIT FUNCTION
The ADM1170 features a fast response current control loop that
actively limits the current by reducing the gate voltage of the
external FET. This current is measured by monitoring the
voltage drop across an external sense resistor. The ADM1170
tries to regulate the gate of the FET to achieve a 50 mV voltage
drop across the sense resistor.
CALCULATING THE CURRENT LIMIT
The sense resistor connected between SENSE+ and the SENSE−
pin is used to determine the nominal fault current limit. This is
given by the following equation:
ILIMITNOM = VCBNOM/RSENSENOM
(1)
The minimum load current is given by Equation 2
ILIMITMIN = VCBMIN/RSENSEMAX
(2)
The maximum load current is given by Equation 3.
ILIMITMAX = VCBMAX/RSENSEMIN
(3)
For proper operation, the minimum current limit must exceed
the circuit maximum operating load current with margin. The
sense resistor power rating must exceed
(VCBMAX)2/RSENSEMIN
CIRCUIT BREAKER FUNCTION
When the supply experiences a sudden current surge, such as a
low impedance fault on load, the bus supply voltage can drop
significantly to a point where the power to an adjacent card is
affected, potentially causing system malfunctions. The
ADM1170 limits the current drawn by the fault by reducing the
Rev. A | Page 11 of 16

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