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ADG787 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer ADG787
Beschreibung 2.5 OHM CMOS Low Power Dual 2:1 Mux/Demux USB 1.1 Switch
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 16 Seiten
ADG787 Datasheet, Funktion
www.DataSheet4U.com
2.5 Ω CMOS Low Power
Dual 2:1 Mux/Demux USB 1.1 Switch
ADG787
FEATURES
USB 1.1 signal switching compliant
−3 dB bandwidth, 150 MHz
Tiny 10-lead LFCSP and MSOP packages, 10-ball WLCSP
package
Single-supply 1.8 V to 5.5 V operation
Low on resistance
2.5 Ω typical
3.45 Ω maximum at 85°C
Typical power consumption: <0.1 μW
APPLICATIONS
USB 1.1 signal switching circuits
Cellular phones
PDAs
MP3 players
Battery-powered systems
Headphone switching
Audio and video signal routing
Communications systems
GENERAL DESCRIPTION
The ADG787 is a low voltage, CMOS device that contains two
independently selectable single-pole, double-throw (SPDT)
switches. It is designed as a general analog-to-digital switch and
can also be used for routing USB 1.1 signals.
This device offers low on resistance of typically 2.5 Ω, making
the part an attractive solution for applications that require low
distortion through the switch.
The ADG787 comes in a 10-ball WLCSP, a tiny 10-lead LFCSP,
and a tiny 10-lead MSOP. These packages make the ADG787
the ideal solution for space-constrained applications.
Each switch conducts equally well in both directions when on
and has an input signal range that extends to the supplies. The
ADG787 exhibits break-before-make switching action.
FUNCTIONAL BLOCK DIAGRAM
ADG787
S1A
D1
S1B
IN1
IN2
S2A
D2
S2B
SWITCHES SHOWN
FOR A LOGIC 0 INPUT
Figure 1.
MASK: FS (12Mbps)
1
20.0ns/DIV
VIN = 3V p-p
TA = 25°C
Figure 2. Eye Pattern; 12 Mbps, VDD = 4.2 V, PRBS 31
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.






ADG787 Datasheet, Funktion
ADG787
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
VDD 1
10 S2A
S1A 2 ADG787 9 D2
D1 3 TOP VIEW 8 IN2
IN1 4 (Not to Scale) 7 S2B
S1B 5
6 GND
Figure 3. 10-Lead LFCSP and 10-lead MSOP Pin Configuration
abc
1
S1B GND S2B
2
IN1 IN2
3
D1 D2
4
S1A VDD S2A
TOP VIEW
(BALLS AT THE BOTTOM)
Figure 4. 10-Ball WLCSP Pin Configuration
Table 4. 10-Lead LFCSP/MSOP Pin Function Descriptions
Pin
No. Mnemonic Description
1 VDD
Most Positive Power Supply Potential.
2 S1A
Source Terminal. May be an input or
output.
3 D1
Drain Terminal. May be an input or
output.
4 IN1
Logic Control Input.
5 S1B
Source Terminal. May be an input or
output.
6 GND
Ground (0 V) Reference.
7 S2B
Source Terminal. May be an input or
output.
8 IN2
Logic Control Input.
9 D2
Drain Terminal. May be an input or
output.
10 S2A
Source Terminal. May be an input or
output.
Table 5. 10-Lead WLCSP Pin Function Descriptions
Ball
Location Mnemonic Description
1a S1B
Source Terminal. May be an input or
output.
1b GND Ground (0 V) Reference.
1c S2B
Source Terminal. May be an input or
output.
2a IN1
Source Terminal. May be an input or
output.
2c IN2
Logic Control Input.
3a D1
Drain Terminal. May be an input or
output.
3c D2
Drain Terminal. May be an input or
output.
4a S1A
Logic Control Input.
4b VDD
Most Positive Power Supply Potential.
4c S2A
Source Terminal. May be an input or
output.
TRUTH TABLE
Table 6.
Logic (IN1/IN2)
0
1
Switch 1A/2A
Off
On
Switch 1B/2B
On
Off
Rev. A | Page 6 of 16

6 Page









ADG787 pdf, datenblatt
ADG787
VDD
0.1μF
VDD
NC
S1B S1A
50Ω
D
GND
NETWORK
ANALYZER
50Ω
VS
RL VOUT
50Ω
OFF ISOLATION = 20 LOG VOUT
VS
Figure 34. Off Isolation
VDD
0.1μF
VOUT
RL
50Ω
50Ω
VS
S1A
VDD
S1B D
RL
50Ω
GND
CHANNEL-TO-CHANNEL CROSSTALK = 20 LOG VOUT
VS
Figure 35. Channel-to-Channel Crosstalk (S1A to S1B)
VDD
0.1μF
VDD
S1B S1A
D
GND
NETWORK
ANALYZER
50Ω
VS
VOUT
RL
50Ω
INSERTION LOSS = 20 LOG
VOUT WITH SWITCH
VOUT WITHOUT SWITCH
Figure 36. Bandwidth
NETWORK
ANALYZER
VOUT
50Ω
S2A
S2B
D2
NC
S1A D1
50Ω
VS S1B NC 50Ω
CHANNEL-TO-CHANNEL CROSSTALK = 20 LOG VOUT
VS
Figure 37. Channel-to-Channel Crosstalk (S1A to S2A)
Rev. A | Page 12 of 16

12 Page





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